EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 48

• Manufacturer Part Number: EZ80L92AZ050SG
• Description: IC WEBSERVER 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80L92AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80L92x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80L920210ZCO
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3878; EZ80L92AZ050SG

PS013014-0107
GPIO Control Registers
edge-triggered interrupt, writing a 1 to that pin’s Port x Data register causes a reset of the
edge-detected interrupt. You must set the bit in the Port x Data register to 1 before entering
either single or dual edge-triggered interrupt mode for that port pin.
When configured for dual edge-triggered interrupt mode (GPIO Mode 6), both a rising
and a falling edge on the pin cause an interrupt request to be sent to the eZ80 CPU.
When configured for single edge-triggered interrupt mode (GPIO Mode 9), the value in
the Port x Data register determines if a positive or negative edge causes an interrupt
request. A 0 in the Port x Data register bit sets the selected pin to generate an interrupt
request for falling edges. A 1 in the Port x Data register bit sets the selected pin to generate
an interrupt request for rising edges.
The 12 GPIO Control Registers operate in groups of four with a set for each Port (Ports B,
C, and D). Each GPIO port features a Port Data register, Port Data Direction register, Port
Alternate register 1, and Port Alternate register 2.
Port x Data Registers
When the port pins are configured for one of the output modes, the data written to the
Port x Data Registers (see
reading from the Port x Data registers always returns the current sampled value of the
corresponding pins. When the port pins are configured as edge-triggered interrupt sources,
writing 1 to the corresponding bit in the Port x Data register clears the interrupt signal that
is sent to the eZ80 CPU. When the port pins are configured for edge-selectable interrupts
or level-sensitive interrupts, the value written to the Port x Data register bit selects the
interrupt edge or interrupt level. See
Table 7. Port x Data Registers (PB_DR = 009Ah, PC_DR = 009Eh, PD_DR =
Bit
Reset
CPU Access
Note: X = Undefined; R/W = Read/Write.
00A2h)
R/W
X
7
Table
R/W
6
X
7) are driven on the corresponding pins. In all modes,
Table
R/W
5
X
6.
R/W
X
4
R/W
X
3
General-Purpose Input/Output
Product Specification
R/W
X
2
eZ80L92 MCU
R/W
X
1
R/W
X
0
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