EZ80L92AZ050SG Zilog, EZ80L92AZ050SG Datasheet - Page 62

IC WEBSERVER 50MHZ 100LQFP

EZ80L92AZ050SG

Manufacturer Part Number
EZ80L92AZ050SG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet

Specifications of EZ80L92AZ050SG

Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3878
EZ80L92AZ050SG

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Manufacturer
Quantity
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EZ80L92AZ050SG
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Part Number:
EZ80L92AZ050SG
Manufacturer:
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eZ80L92 MCU
Product Specification
56
T1
T2
T
T3
CLK
System Clock
ADDR[23:0]
DATA[7:0]
CSx
RD
WAIT
WR
MREQ
or IORQ
®
Figure 8. Z80
Bus Mode Write Timing Example
Intel Bus Mode
Chip selects configured for Intel Bus Mode modify the eZ80 bus signals to duplicate a
four-state memory transfer similar to that found on Intel-style microprocessors. The bus
signals and eZ80L92 pins are mapped as illustrated in
Figure
9. In Intel Bus Mode, the
user can select either multiplexed or non-multiplexed address and data buses. In non-mul-
tiplexed operation, the address and data buses are separate. In multiplexed operation, the
lower byte of the address, ADDR[7:0], also appears on the data bus, DATA[7:0], during
State T1 of the Intel Bus Mode cycle. During multiplexed operation, the lower byte of the
address bus also appears on the address bus in addition to the data bus.
PS013014-0107
Chip Selects and Wait States

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