Z8S18020FSG Zilog, Z8S18020FSG Datasheet - Page 21

IC Z180 MPU 80-QFP

Z8S18020FSG

Manufacturer Part Number
Z8S18020FSG
Description
IC Z180 MPU 80-QFP
Manufacturer
Zilog
Datasheet

Specifications of Z8S18020FSG

Processor Type
Z180
Features
Enhanced Z180
Speed
20MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
80-BQFP
Processor Series
Z8S180X
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8S18000ZEM
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4541-5
269-4541
Z8S18020FSG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8S18020FSG
Manufacturer:
STM
Quantity:
4 983
Part Number:
Z8S18020FSG
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
Z8S18020FSG1960
Manufacturer:
Zilog
Quantity:
10 000
lowed by execution of the
cannot generate a recovery interrupt.
ZiLOG
This condition provides a technique for synchronization
with high-speed external events without incurring the la-
tency imposed by an interrupt-response sequence. Figure 14
depicts the timing for exiting
rupt request.
case, on-chip I/O (ASCI, CSI/O, PRT) stops operating.
However, the CPU continues to operate. Recovery from
bination of
mode is entered by setting the
chip I/O and CPU stop operating, reducing power consump-
tion, but the
mode except that internal I/O sources (disabled by
mode by performing the following actions:
The oscillator keeps operating but its output is blocked to
all circuitry including the
Set the
Set
Set
Execute the
to
0
.
mode is performed by resetting the
bit of the I/O Control Register (
Software puts the Z8S180/Z8L180 into this
to
to
output continues to operate. Recovery from
mode is the same as recovery from
and
bit (
instruction
mode is entered by setting the
) to
instruction. In this mode, on-
pin. DRAM refresh and all
modes.
mode due to an inter-
bit in
mode is the com-
) to
to
1
. In this
1
bit in
fol-
)
internal devices stop, but external interrupts can occur. Bus
granting to external Masters can occur if the
the CPU control Register (
mode was entered.
The Z8S180/Z8L180 leaves
Low on
external interrupt request on
abled in the INT/TRAP Control Register. As previously de-
scribed for
terrupt request when the
tion, the device starts by performing the interrupt with the
return address of the instruction after the
If an external interrupt enables the INT/TRAP control reg-
ister while the
mode; specifically, the processor restarts by executing the
instructions following the
Figure 15 indicates the timing for exiting
to an interrupt request.
mode due to an
The Z8S180/Z8L180 takes about 9.5 clocks to restart.
The Z8S180/Z8L180 takes about 1.5 clock ticks to re-
start.
, an external interrupt request on
mode, when the Z8S180/Z8L180 leaves
bit is
, or due to an enabled external in-
0
, Z8S180/Z8L180 leaves
flag is
instruction.
) was set to
,
mode in response to a
1
due to an
or
1
instruction.
before
mode due
that is en-
instruc-
, or an
bit in

Related parts for Z8S18020FSG