Z8S18020PSG Zilog, Z8S18020PSG Datasheet - Page 60

• Manufacturer Part Number: Z8S18020PSG
• Description: IC Z180 MPU 64-DIP
• Manufacturer: Zilog

Specifications of Z8S18020PSG

• Processor Type: Z180
• Features: Enhanced Z180
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8S180X
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: Z8S18000ZEM
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4301; Z8S18020PSG

For burst memory to/from memory transfers, the DMAC
takes control of the bus continuously until the DMA transfer
Table 16 indicates all DMA transfer mode combinations of
fers are not implemented, 12 combinations are available.
nel 0 is configured for memory to/from memory transfers
there is no Request Handshake signal to control the transfer
timing. Instead, two automatic transfer timing modes are se-
lectable: burst (
,
* Includes memory mapped I/O.
,
, and
. Because I/O to/from I/O trans-
) and cycle steal (
When chan-
).
completes (as indicated by the byte count register = ). In
cycle steal mode, the CPU is provided a cycle for each DMA
byte transfer cycle until the transfer is completed.
For channel 0 DMA with I/O source or destination, the se-
lected Request signal times the transfer ignoring
is cleared to
0
during
.
ZiLOG
.