Z85C3010PEG Zilog, Z85C3010PEG Datasheet - Page 26

• Manufacturer Part Number: Z85C3010PEG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog

Specifications of Z85C3010PEG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3933; Z85C3010PEG

CMOS SCC Serial Communications Controller
Product Specification
22
station while an SCC operating in regular SDLC mode acts as a controller (see
Figure 11
on page 22). The SDLC loop mode can be selected by setting WR10 bit D1.
Controller
Secondary #1
Secondary #4
Secondary #2
Secondary #3
Figure 11. An SDLC Loop
A secondary station in an SDLC Loop is always listening to the messages sent around the
loop and passes these messages to the rest of the loop by retransmitting them with a one-
bit-time delay. The secondary station places its own message on the loop only at specific
times.
The controller signals that secondary stations can transmit messages by sending a special
character, called an End Of Poll (EOP), around the loop. The EOP character is the bit
pattern 11111110. Because of zero insertion during messages, this bit pattern is unique
and easily recognized.
When a secondary station contains a message to transmit and recognizes an EOP on the
line, it changes the last binary 1 of the EOP to a 0 before transmission. This change has the
effect of turning the EOP into a flag sequence. The secondary station now places its mes-
sage on the loop and terminates the message with an EOP. Any secondary stations further
down the loop with messages to transmit append their messages to the message of the first
secondary station by the same process. Any secondary stations without messages to send
echo the incoming message and are prohibited from placing messages on the loop (except
when recognizing an EOP). In SDLC Loop mode, NRZ, NRZI, and FM coding can be
used.
The SCC’s ability to receive high speed back-to-back SDLC frames is maximized by a 10-
deep by 19-bit wide status FIFO. When enabled (through WR15, bit D2), it provides the
DMA the ability to continue to transfer data into memory so that the CPU can examine the
message later. For each SDLC frame, a 14-bit byte count and 5 status/error bits are stored.
The byte count and status bits are accessed through Read Registers 6 and 7. Read Regis-
ters 6 and 7 are only accessible when the SDLC FIFO is enabled. The 10 x 19 status FIFO
is separate from the 3-byte receive data FIFO.
PS011705-0608
Functional Description