Z85C3010PEG Zilog, Z85C3010PEG Datasheet - Page 29

• Manufacturer Part Number: Z85C3010PEG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog

Specifications of Z85C3010PEG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3933; Z85C3010PEG

CMOS SCC Serial Communications Controller
Product Specification
25
internal receive data and RxD is ignored (except to be echoed out through TxD). The CTS
and DCD inputs are also ignored as transmit and receive enables. However, transitions on
these inputs can still cause interrupts. Local Loopback works in Asynchronous, Synchro-
nous and SDLC modes with NRZ, NRZI or FM coding of the data stream.
SDLC FIFO Frame Status FIFO Enhancement
The SCC’s ability to receive high speed back-to-back SDLC frames is maximized by a
10-deep by 19-bit wide status FIFO. When enabled (through WR15, bit D2), it provides
the DMA the ability to continue to transfer data into memory so that the CPU can examine
the message later. For each SDLC frame, a 14-bit byte count and 5 status/error bits are
stored. The byte count and status bits are accessed through Read Registers 6 and 7. Read
Registers 6 and 7 are only accessible when the SDLC FIFO is enabled. The 10x19 status
FIFO is separate from the 3-byte receive data FIFO.
When the enhancement is enabled, the status in Read Register 1 (RR1) and byte count for
the SDLC frame are stored in the 10 x 19 bit status FIFO. This arrangement allows the
DMA controller to transfer the next frame into memory while the CPU verifies that the
message was properly received.
Summarizing the operation; data is received, assembled, and loaded into the eight byte
FIFO before being transferred to memory by the DMA controller. When a flag is received
at the end of an SDLC frame, the frame byte count from the 14-bit counter and five status
bits are loaded into the status FIFO for verification by the CPU. The CRC checker auto-
matically resets in preparation for the next frame which can begin immediately. Since the
byte count and status are saved for each frame, the message integrity is verified at a later
time. The status information for up to 10 frames is stored before a status FIFO overrun
occurs.
If a frame is terminated with an ABORT, the byte count is loaded to the status FIFO and
the counter resets for the next frame.
FIFO Detail
For more details on the FIFO operation details, see
Figure 13
on page 26.
Enable/Disable
This FIFO is implemented is enabled when WR15, bit D2, is set and the SCC is in the
SDLC/HDLC mode. Otherwise, the status register contents bypass the FIFO and go
directly to the bus interface (the FIFO pointer logic is reset either when disabled or
through a channel or Power-On Reset). When the FIFO mode is disabled, the SCC is
downward compatible with the NMOS Z8530. The FIFO mode is disabled on power-up
(WR15 D2 is set to 0 on reset). The effects of backward compatibility on the register set
are that RR4 is an image of RR0, RR5 is an image of RR1, RR6 is an image of RR2 and
RR7 is an image of RR3. For more details on the added registers, see
Figure 16
on page
30. The status of the FIFO Enable signal is obtained by reading RR15, bit D2. If the FIFO
is enabled, the bit is set to 1; otherwise, it resets.
PS011705-0608
Functional Description