Z85C3010PEG Zilog, Z85C3010PEG Datasheet - Page 30

• Manufacturer Part Number: Z85C3010PEG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog

Specifications of Z85C3010PEG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3933; Z85C3010PEG

PS011705-0608
Interface
to SCC
Read Operation
When WR15 bit D2 sets and the FIFO is not empty, the next read to status register RR1 or
registers RR7 and RR6, is from the FIFO. Reading status register RR1 causes one location
of the FIFO to become empty. Status is read after reading the byte count, otherwise the
count is incorrect. Before the FIFO underflows, it is disabled. In this case, the multiplexer
is switched allowing status to read directly from the status register. Reads from RR7 and
RR6 contain bits that are undefined. Bit D6 of RR7 (FIFO Data Available) determines if
status data is coming from the FIFO or directly from the status register, which sets to 1
when the FIFO is not empty. Not all status bits are stored in the FIFO. The All Sent, Parity,
and EOF bits bypass the FIFO. Status bits sent through the FIFO are Residue Bits (3),
Overrun, and CRC Error.
RR1
– All Sent bypasses MUX and equals contents of SCC Status Register
– Parity Bits bypasses MUX and does the same
– EOF is set to 1 whenever reading from the FIFO
In SDLC Mode the following definitions apply
2 Bits
6-Bit MUX
Overrun, CRC Error
5 Bits
SCC Status Reg
Residue Bits (3)
Figure 13. SDLC Frame Status FIFO
6 Bits
RR1
10 Deep by 19 Bits Wide
5 Bits
Bit 7 Bit 6
FIFO Array
EOF = 1
RR7 D7
FIFO Overflow Status Bit
MSB pf RR(7) is set on Status FIFO overflow
Frame Status FIFO Circuitry
RR7 D6
FIFO Data available status bit Status Bit set to 1
When reading from FIFO
Bits 5-0
Byte Counter
CMOS SCC Serial Communications Controller
6 Bits
14 Bits
RR7 D5-D0 + RR6 D7-D0
Byte Counter Contains 14 bits
for a 16 KByte maximum count
RR6
8 Bits
EN
End of Frame Signal
Status Read Comp
Increment on Byte Detection
Reset on Flag Detect
Enable Count in SDLC
Over
4-Bit Comparator
4-Bit Counter
4-Bit Counter
Head Pointer
Tail Pointer
Equal
WR(15) Bit 2
Set Enables
Status FIFO
FIFO Enable
Product Specification
Functional Description
26