Manufacturer Part NumberZ8S18020VEG1960
DescriptionIC Z180 MPU 68-PLCC
Z8S18020VEG1960 datasheet

Specifications of Z8S18020VEG1960

Processor TypeZ180FeaturesEnhanced Z180
Mounting TypeSurface MountPackage / Case68-LCC (J-Lead)
Processor SeriesZ8S180XCoreZ80
Data Bus Width8 bitMaximum Clock Frequency20 MHz
Number Of Timers2Operating Supply Voltage0 V to 3.3 V
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
Development Tools By SupplierZ8S18000ZEMMinimum Operating Temperature- 40 C
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names269-4304
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Code Compatible with ZiLOG Z80
Extended Instructions
Two Chain-Linked DMA Channels
Low Power-Down Modes
On-Chip Interrupt Controllers
Three On-Chip Wait-State Generators
On-Chip Oscillator/Generator
Expanded MMU Addressing (Up to 1 MB)
Clocked Serial I/O Port
The enhanced Z8S180/Z8L180
significantly improves on
previous Z80180 models, while still providing full back-
ward compatibility with existing ZiLOG Z80 devices. The
Z8S180/Z8L180 now offers faster execution speeds, pow-
er-saving modes, and EMI noise reduction.
This enhanced Z180
design also incorporates additional
feature enhancements to the ASCIs, DMAs, and
mode power consumption. With the addition of ESCC-like
Baud Rate Generators (BRGs), the two ASCIs offer the flex-
ibility and capability to transfer data asynchronously at rates
of up to 512 Kbps. In addition, the ASCI receiver features
a 4-byte first in/first out (FIFO) buffer which reduces the
likelihood of overrun errors. The DMAs have been modified
to allow for chain-linking of the two DMA channels when
set to take their DMA requests from the same peripherals
device. This feature allows for nonstop DMA operation be-
tween the two DMA channels.
Not only does the Z8S180/Z8L180 consume less power dur-
ing normal operations than the previous model, it offers
Two 16-Bit Counter/Timers
Two Enhanced UARTs (up to 512 Kbps)
Clock Speeds: 10, 20, 33 MHz
Operating Range: 5V (3.3V@ 20 MHz)
Operating Temperature Range: 0°C to +70°C
–40°C to +85°C Extended Temperature Range
Three Packaging Styles
68-Pin PLCC
64-Pin DIP
80-Pin QFP
three modes intended to further reduce power consumption.
Power consumption during
10 A by stopping the external oscillators and internal
clock. The
into a stopped state, consuming less current while the on-
chip I/O devices still operate. The
places both the CPU and the on-chip peripherals into a
stopped mode, reducing power consumption even further.
A new clock-doubler feature in the Z8S180/Z8L180 allows
the internal clock speed to be twice the external clock speed.
As a result, system cost is reduced by allowing the use of
lower-cost, lower-frequency crystals.
The Enhanced Z180 is housed in 80-pin QFP, 68-pin PLCC,
and 64-pin DIP packages.
All Signals with an overline are active Low. For exam-
ple: B/W, in which WORD is active Low; or B/W, in
which BYTE is active Low.
Mode is reduced to
mode reduces power by placing the CPU

Z8S18020VEG1960 Summary of contents

  • Page 1

    ... Clocked Serial I/O Port ™ The enhanced Z8S180/Z8L180 significantly improves on previous Z80180 models, while still providing full back- ward compatibility with existing ZiLOG Z80 devices. The Z8S180/Z8L180 now offers faster execution speeds, pow- er-saving modes, and EMI noise reduction. ™ This enhanced Z180 ...

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    ... Power connections follow the conventional descriptions be- low: ZiLOG ...

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    ... ZiLOG ...

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    ... ZiLOG ...

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    ... ZiLOG Address Bus (Output, 3-state). 20-bit address bus. The Address Bus provides the address for memory data bus exchanges ( MB) and I/O data bus exchanges ( KB). The address bus enters a high–impedance state during reset and external bus ac- knowledge cycles. Address line output of PRT channel 1 ( ...

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    ... Transfer End 0 and 1 (Outputs, active is multiplexed with is the output from PRT of the address Transmit Data 0 and 1 (Outputs). These sig- indicates to the (and subsequent states). If the input is states are inserted input is sampled High, at which time exe- (Output, active Low, 3-state). indicates that ZiLOG . DC Char- ...

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    ... ZiLOG ...

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    ... The time base for the counters is derived from the system clock (divided by 20) before reaching the counter. PRT channel 1 provides an op- tional output to allow for waveform generation. ZiLOG This logic consists ...

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    ... ZiLOG The CSI/O channel provides a half-duplex serial transmitter and receiver. This channel can be used for simple high-speed data connection to an- other microprocessor or microcomputer. both CSI/O transmission and reception. Thus, the system design must ensure that the constraints of half-duplex op- eration are met (Transmit and Receive operation cannot oc- cur simultaneously) ...

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    ... ZiLOG ...

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    ... ZiLOG is descended from two different “ancestor” processors, ZiLOG’s original Z80 and the Hitachi 64180. The Operat- ing Mode Control Register (OMCR), illustrated in Figure 8, can be programmed to select between certain Z80 and 64180 differences. The Z8S180/Z8L180 set to a When code fetch cycles, Interrupt Acknowledge cycles, and the ...

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    ... When ing the next opcode fetch cycle regardless of the state pro- grammed into the tary (one time) and it is not necessary to preprogram a to disable the function (see Figure 10 ZiLOG signal. When = , there signal, and controls = , the ...

  • Page 19

    ... ZiLOG When = , the timing of the 0 the timing of the Z80. The and as a result of the rising edge of T2. (Figure 12.) Z8S180/Z8L180 can operate in seven modes with respect to activity and power consumption: Normal Operation Mode Mode Mode Mode Mode Mode (with or without ) and signals match ...

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    ... DI instruction), the Z8S180/Z8L180 leaves mode in response to a ing the following instruction(s). instruction. The program can either instruction to wait for another in- Interrupt Acknowledge Cycle external request on . mode interrupt bit is instruction mode by simply execut- ZiLOG , so that 1 bit is 0 ...

  • Page 21

    ... ZiLOG This condition provides a technique for synchronization with high-speed external events without incurring the la- tency imposed by an interrupt-response sequence. Figure 14 depicts the timing for exiting rupt request. mode is entered by setting the bit of the I/O Control Register ( case, on-chip I/O (ASCI, CSI/O, PRT) stops operating. ...

  • Page 22

    ... Master if the BREXT bit (CCR5 depicts the timing for this sequence. A response to a bus request takes 8 clock cycles longer than in normal operation. mode, it grants the bus After the external Master negates the Bus Request, the . Figure Z8S180/Z8L180 disables the 1 mode. ZiLOG clock and remains in ...

  • Page 23

    ... ZiLOG Software can put the Z8S180/Z8L180 into this mode by set- ting the bit (ICR5 CCR6 to 1 the instruction. This mode stops the on-chip oscillator and thus draws the least power of any mode, less than 10µA. As with mode, the Z8S180/Z8L180 leaves mode in response to a Low on on – ...

  • Page 24

    ... CCR3 bit. The latter (not the bit ( ) external Masters. If so, can be used. instruction. If goes inactive before the end of the clock stabiliza- The Z8S180/Z8L180 takes either clocks to restart, depending on the CCR3 bit. ) case may be prohibitive for many demand-driven ZiLOG , or mode. mode 17 (131,072) or mode ...

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    ... ZiLOG ...

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    ... Ordering Information ature ranges and product numbers. Find package drawings in Package Information. Permanent damage may occur if maximum ratings are exceeded. Normal operation should be under recom- mended operating conditions. If these conditions are ex- ceeded, it could affect reliability. DC Char- lists temper- ZiLOG ...

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    ... ZiLOG ...

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    ... ZiLOG ...

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    ... ZiLOG ...

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    ... ZiLOG ...

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    ... ZiLOG  ...

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    ... ZiLOG ...

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    ... and the part honored after the clock stabilization This bit controls the drive capability on the , the Clock output 1 ZiLOG ) and ...

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    ... ZiLOG This bit controls the drive capability of certain external I/O pins of the Z8S180/Z8L180. When this bit is set to , the output drive capability of the following pins is 1 reduced to 33 percent of the original drive capability: This bit controls the drive capability of the CPU Control pins. When this bit is set to ...

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    ... This register is not program-accessible into and Register is transferred to the Data can be written while byte of data. Thus, the ASCI transmitter is double buffered. idles by outputting a continuous High level. Data written to the ASCI Transmit Data as soon as is shifting out the previous ZiLOG is empty. ...

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    ... ZiLOG Data can be written into and read from the ASCI Transmit Data Register. If data is read from the ASCI Transmit Data Register, the ASCI data transmit operation is not affected by this operation. receives data shifted in on the automatically transferred to the ASCI Receive Data Regis- ter ( ) empty ...

  • Page 42

    ... When written to , the function is selected to reset all error flags and in the / is undefined during These bits program the ASCI data format as follows. is cleared function. allows The data formats available based on all combinations Register and are indicated in Table 9. ZiLOG ...

  • Page 43

    ... ZiLOG processor communication format is selected ( is used to specify the data bit for transmission then is transmitted then is transmitted. The 0 0 fined during and after . the data format is configured for multiprocessor mode based on (number of data bits) and bits The format is as follows: Multiprocessor ( ) format offers no provision for parity ...

  • Page 44

    ... A framing error is detected to the bit in the 1 is also cleared by in pin is auto-enabled and is negated is set, but only if neither DMA channel are is and are ZiLOG register bit in the cleared reg- mode should be set to is and , then ASCI1 is , either ...

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    ... ZiLOG requests an interrupt when cleared when the pin is High cleared following the pin’s transition from High to Low and during . When bit 6 of the ister is to select auto-enabling, and the pin is negated 0 (High), the receiver is reset and its operation is inhibited. tures an external ...

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    ... A CSI/O transmit operation to . When is set to 1 pin. In external clock mode, pin. In either case, data is shift- pin synchronous with the (internal or ex sets ZiLOG and , the data and re- 1 and are ...

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    ... ZiLOG never both set to at the same time. 1 during and mode. and select the CSI/O transmit/receive clock source and speed. , and are all set to Table 11 indicates CSI/O Baud Rate Selection. After , the pin is configured as an external clock input ( ). Changing these values causes to become an output pin and the selected clock is output when transmit or receive operations are enabled ...

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    ... When is set and and and using the multiplexed , down-counting is stopped and 1 , written. reg- for . , the pin can be forced High, decrements to enable and disable down-counting for , respectively. When ( is freely read or and are cleared to during 0 does not decrement until is set to . ZiLOG . set to and ...

  • Page 49

    ... ZiLOG The ASCI Extension Control Registers ( ) control functions that have been added to the the pin auto-enables the ASCI0 receiver, such that when the pin is negated/High, the Receiver is held in a state. If this bit is , the state of the 1 effect on receiver operation. In either state of this bit, soft- ...

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    ... ZiLOG ...

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    ... ZiLOG If the bits of the register are not the mode bit in the register is vides the clock by two times the registers’ 16-bit value, plus two result, the clock is presented to the transmitter and receiver for division by 1, 16, or 64, and is output on the pin. If the ...

  • Page 52

    ... The default for this bit is When this bit is set Setting this bit Operating restrictions for device operation are listed be- low low-noise option is required, and normal device operation is required, use the clock multiplier feature. ZiLOG en- 1 and pins and pins. ...

  • Page 53

    ... ZiLOG The DMA Source Address Register Channel 0 specifies the physical source address for channel 0 transfers. The register contains 20 bits and can specify up to 1024 KB memory ad- dresses 64-KB I/O addresses. Channel 0 source can be memory, I/O, or memory mapped I/O. For I/O, bits of this register identify the Request Handshake sig- nal ...

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    ... Channel 0 destination can be memory, I/O, or memory mapped I/O. For I/O, the identify the Request Handshake signal for channel 0. bits of this register If the DMA destination is in I/O space, bits ister select the DMA request signal for DMA0, as follows: ZiLOG of this reg- ...

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    ... ZiLOG The DMA Byte Count Register Channel 0 specifies the number of bytes to be transferred. This register contains 16 bits and may specify up to 64-KB transfers. When one byte is transferred, the register is decremented by one. If bytes should be transferred, must be stored before the DMA op- eration. All DMA Count Register channels are undefined during ...

  • Page 56

    ... The DMA Memory Address Register Channel 1 specifies the physical memory address for channel 1 transfers. The address may be a destination or a source memory location. The register contains 20 bits and may specify up to 1024 KB memory addresses. ZiLOG ...

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    ... ZiLOG The DMA I/O Address Register specifies the I/O device for channel 1 transfers. This address may be a destination or source I/O device. and bits. The most significant byte identifies the Request Hand- shake signal and controls the Alternating Channel feature. The channels are programmed for the same I/O source or I/O destination ...

  • Page 58

    ... DMA 0 interrupt service routine. To restart and/or should be written with allowing DMA operations to continue. 1 cannot be directly written. The bit is cleared indirectly set to by setting cleared to during 1 0 ZiLOG during during 0 , for 0 (even 1 0 and/or . ...

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    ... ZiLOG The DMA Mode Register ( dressing and transfer mode for channel 0. mode specifies whether the destination for channel 0 transfers is memory or I/O, and whether the address should be incre- mented or decremented for each byte transferred. are cleared to during used to set the ad- This mode specifies whether the source for channel 0 transfers ...

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    ... In cycle steal mode, the CPU is provided a cycle for each DMA byte transfer cycle until the transfer is completed. For channel 0 DMA with I/O source or destination, the se- ). lected Request signal times the transfer ignoring is cleared to ZiLOG during . 0 . ...

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    ... ZiLOG The DMA/WAIT Control Register ( insertion of wait states into DMAC (and CPU) accesses of memory or I/O. Also, the register defines the Request signal bit specifies the number of wait states introduced into CPU or DMAC memory access cycles. to during . 1 fies the number of wait states introduced into CPU or DMAC I/O access cycles ...

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    ... Z8S180/Z8L180: bit in the Interrupt . 1 If logical address 0000H is mapped to physical address 00000H, the vector is the same as for case, testing the bit in reveals whether the re- start at physical address 00000H was caused ZiLOG during 0 and clears may occur during /Control ( ) . this ...

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    ... ZiLOG All occur after fetching an undefined second opcode byte following one of the prefix opcodes ( after fetching an undefined third opcode byte FDH following one of the double-prefix opcodes ( ). FDCBH The state of the Undefined Fetch Object ( , , , allows software to correctly CBH DDH EDH pending on whether the second or third byte of the opcode ...

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    ... ZiLOG ...

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    ... ZiLOG The Refresh Control Register ( and length of refresh cycles, while enabling or disabling the refresh function. *calculated interval. After initialized value of , refresh cycles occur with an inter- val of 10 clock cycles and be 3 clock cycles in duration. 1. Refresh Cycle insertion is stopped when the CPU is in the following states: a ...

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    ... Z8S180/Z8L180 64-KB logical address ) specifies the base ad- ical address for Common Area 1 accesses. All bits of are reset to dress for Bank Area accesses. All bits of during 0 ) specifies bound- space for up to three areas; Common Area), Bank Area and Common Area 1. during . 0 . ZiLOG are reset to ...

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    ... Bank Area. All bits of are set to 1 The Z8S180/Z8L180 is descended from two different an- cestor processors, ZiLOG’s original Z80 and the Hitachi 64180. The Operating Mode Control Register ( be programmed to select between certain differences be- tween the Z80 and the 64180. T ...

  • Page 68

    ... I/O addresses. also controls the enabling and dis- abling of mode (Figure 83). relocate internal I/O as indicated in Figure 84. when is set to . Normal I/O operation resumes when 1 is reprogrammed mode is enabled The high-order 8 bits of 16-bit internal I/O address are al- . ways and are cleared to 0 ZiLOG during . 0 ...

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    ... ZiLOG ...

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    ... ZiLOG ...

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    ... For fast results, contact your local ZiLOG sales office for assistance in ordering the part(s) required. with some aspects of the document may be found, either by ZiLOG or its customers in the course of further application and characterization work. In addition, ZiLOG cautions that delivery may be uncertain at times, due to start-up yield issues. ...