MPC852TCVR66A Freescale Semiconductor, MPC852TCVR66A Datasheet - Page 21

• Manufacturer Part Number: MPC852TCVR66A
• Description: IC MPU POWERQUICC 66MHZ 256PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC852TCVR66A

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 66MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC852TADS-KIT
• Maximum Clock Frequency: 66 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.9/3.465V
• Operating Supply Voltage (min): 1.7/3.135V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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Freescale Semiconductor
B35b
Num
B36
B37
B38
B39
B40
B41
B42
B43
If the rate of change of the frequency of EXTAL is slow (that is, it does not jump between the minimum and maximum values
in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time), then the maximum
allowed jitter on EXTAL can be up to 2%.
For part speeds above 50MHz, use 9.80ns for B11a.
The timing required for BR input is relevant when the MPC852T is selected to work with internal bus arbiter. The timing for BG
input is relevant when the MPC852T is selected to work with external bus arbiter.
For part speeds above 50MHz, use 2ns for B17.
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is
asserted.
For part speeds above 50MHz, use 2ns for B19.
The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read
accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats where DLT3 = 1 in the
UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
This formula applies to bus operation up to 50 MHz.
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37 and
B38 are specified to enable the freeze of the UPM output signals as described in
The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified
in
Figure
A(0:31), BADDR(28:30), and D(0:31) to
BS valid - as requested by control bit BST2
in the corresponding word in the UPM
(MIN = 0.75 × B1 – 2.00)
A(0:31), BADDR(28:30), and D(0:31) to
GPL valid as requested by control bit GxT4
in the corresponding word in the UPM
(MIN = 0.25 × B1 – 2.00)
UPWAIT valid to CLKOUT falling edge
(MIN = 0.00 × B1 + 6.00)
CLKOUT falling edge to UPWAIT valid
(MIN = 0.00 × B1 + 1.00)
AS valid to CLKOUT rising edge
(MIN = 0.00 × B1 + 7.00)
A(0:31), TSIZ(0:1), RD/WR, BURST, valid
to CLKOUT rising edge
(MIN = 0.00 × B1 + 7.00)
TS valid to CLKOUT rising edge (setup
time) (MIN = 0.00 × B1 + 7.00)
CLKOUT rising edge to TS valid (hold
time) (MIN = 0.00 × B1 + 2.00)
AS negation to memory controller signals
negation (MAX = TBD)
22.
Characteristic
MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
Table 9. Bus Operation Timings (continued)
11
10
10
20.70
5.60
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
33 MHz
Max
TBD
—
—
—
—
—
—
—
—
16.70
4.30
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
40 MHz
Max
TBD
—
—
—
—
—
—
—
—
Figure
13.00
3.00
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
50 MHz
19.
TBD
Max
—
—
—
—
—
—
—
—
9.40
1.80
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
66 MHz
Bus Signal Timing
Max
TBD
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
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