MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet

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... SerDes block, an enhanced local bus controller (eLBC), an integrated programmable interrupt controller (IPIC), a general purpose DMA controller, two I UART (DUART), GPIOs, USB, general purpose timers, and © Freescale Semiconductor, Inc., 2011. All rights reserved. Document Number: MPC8308EC 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 2 3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 ...

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... USB 2.0 HS Host/Device/OTG x1 Figure 1. MPC8308 Block Diagram Table 1. Absolute Maximum Ratings Symbol DD1 Enhanced DDR2 Local Bus DMA Controller eTSEC1 RGMII,MII RGMII,MII ULPI 1 Max Value Unit –0.3 to 1.26 –0.3 to 1.26 DD2 –0.3 to 1.9 –0.3 to 3.6 Freescale Semiconductor eTSEC2 Notes V — V — V — ...

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... Characteristic SerDes internal digital power SerDes internal digital power SerDes I/O digital power SerDes analog power for PLL SerDes analog power for PLL SerDes I/O digital power MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Symbol XCOREV DD XPADV DD SDAV DD LV ...

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... V ± 100 mV DD GVDD/2 (0.49 × REF DD 0.51 × 3.3 V ± 300 2.5 V ± 125 mV DD2 3.3 V ± 300 Standard = 0 to 105 A J Extended = -40 to 105 and not necessarily the voltage from the ball map. J. Freescale Semiconductor 1 Unit °C ...

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... the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before the I/O supplies reach 0.7 V; see MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Not to Exceed 10 interface refers to the clock period associated with the bus clock interface. ...

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... CSB Frequency (MHz) Typical 133 133 133 , XPADV , and SDAV ) 105° C μ s, this requirement is for ESD , LV , and Core Voltage ( 0 SYS_CLK_IN Maximum Unit 530 900 mW 565 950 mW 600 1000 mW ) and PLL (AV DD DD1, = 1.0 V and ambient temperature = 1. junction DD Freescale Semiconductor Table 4. ...

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... Input low voltage SYS_CLK_IN input current Table 7 provides the RTC clock input (RTC_PIT_CLOCK) DC electrical specifications for the device. Table 7. RTC_PIT_CLOCK DC Electrical Characteristics Parameter Input high voltage Input low voltage MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor (1.8 V) (3.3 V) 250 MHz 0.302 — ...

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... Typ Max Unit Notes — 66.67 MHz — 41.67 ns 1.2 ns — — ±150 ps Typ Max Unit 32768 — Hz μs — 3 — Max Unit 0.8 V μA ±5 — V Freescale Semiconductor 1, 6 — Notes — — — ...

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... SYS_CLK_IN. SYS_CLK_IN 2. POR configuration signals consists of CFG_RESET_SOURCE[0:3]. Table 12 provides the PLL lock times. Parameter/Condition System PLL lock time e300 core PLL lock time MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Symbol Condition Min 8 ...

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... IO C DIO = 1.8 V ± 0.090 MHz 25° (typ Max Unit 1.9 V 0.51 × 0.04 V REF – 0.125 V REF μA 9.9 — mA — (typ)=1 Min Max Unit — 0 /2, V (peak-to-peak) = 0.2 V. OUT DD OUT Freescale Semiconductor Notes — — 4 — — Notes 1 1 ...

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... The amount of skew that can be tolerated from MDQS to a corresponding MDQ or MECC signal is called t be determined by the following equation the absolute value of t CISKEW 3. Memory controller ODT value of 150 Ω is recommended MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor . REF Symbol Min I — ...

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... Figure 4. Timing Diagram for t DISKEW 1 Symbol Min t 7.5 MCK t DDKHAS 266 MHz 2.9 t DDKHAX 266 MHz 2.33 t DDKHCS 266 MHz 2.5 t DDKHCX 266 MHz 3.15 t –0.6 DDKHMH timing parameter. DISKEW t DISKEW Max Unit 10 ns — ns — ns — ns — ns 0.6 ns Freescale Semiconductor Notes ...

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... The data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t symbol conventions described in note 1. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor 1 Symbol Min ...

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... MDQ[x]/ MECC[x] Figure 6. DDR2 SDRAM Output Timing Diagram MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev MCK t DDKHMHmax DDKHMH(min) = –0.6 ns Figure 5. Timing Diagram for t DDKHMH t MCK t ,t DDKHAS DDKHCS t ,t DDKHAX DDKHCX NOOP t DDKHMP t DDKHMH t DDKHDS DDKHDX t DDKHME t DDKLDS t DDKLDX Freescale Semiconductor ...

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... Subsequent bit values are sampled each 16 8 Ethernet: Three-Speed Ethernet, MII Management This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII management. MPC8308 supports dual Ethernet controllers. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor = 50 Ω Figure 7. DDR2 AC Test Load ...

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... Section 8.3, “Ethernet Management Interface Table 21. MII DC Electrical Characteristics Conditions — –4 Min 4 Min OL DD — — — — VSS IN symbol referenced in IN Min Max 3.0 3.6 2. 0.3 DD VSS 0.50 2 0.3 DD –0.3 0.90 — 40 –600 — Table 1 and Table 2. Freescale Semiconductor Table 21 Unit μA μA ...

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... MTX the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of t MTX used with the appropriate letter: R (rise (fall). MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Conditions — –1 ...

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... MII (M) receive (RX) clock. For rise and fall times, the latter convention is t MTXR Min Typ Max — 400 — — 40 — 35 — 65 10.0 — — 10.0 — — 1.0 — 4.0 1.0 — 4.0 symbolizes MII MRDVKH clock reference MRX Freescale Semiconductor Unit ...

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... Data to clock input skew (at receiver) 3 Clock cycle duration 4, 5 Duty cycle for 1000Base-T Duty cycle for 10BASE-T and 100BASE-TX Rise time (20%–80%) Fall time (20%–80%) MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor t MRX t t MRXH MRXF Valid Data t MRDVKH = 50 Ω ...

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... RGMII receive (RX) clock. Note also that the notation for rise RGT t RGTH t SKRGT TXD[8:5] TXD[3:0] TXD[7:4] TXD[9] TXD[4] TXEN TXERR RXD[8:5] RXD[3:0] RXD[7:4] t SKRGT RXD[4] RXD[9] RXDV RXERR — 8.0 — 47 — the lowest speed transitioned RGT t RGT t SKRGT t SKRGT Freescale Semiconductor ns % ...

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... At recommended operating conditions with LV Parameter/Condition MDC frequency MDC period MDC clock pulse width high MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Conditions — –1 1.0 mA ...

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... MDC t t MDCH MDCF t MDDVKH t MDDXKH t MDKHDX Symbol Condition – — IH Max Unit 10 ns symbolizes management MDKHDX t MDCR Min Max 2.4 — — 0.5 — 0.4 2.0 NVDD + 0.3 Freescale Semiconductor Notes — for Unit ...

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... High-level input voltage Low-level input voltage Input current = –100 μA High-level output voltage 100 μA Low-level output voltage Note: 1. The symbol this case, represents the NV IN MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Symbol Condition V — ≤ V ≤ NVDD Symbol t TMRCK ...

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... For example Ω Z Figure 13. USB AC Test Load t USIVKH t USKHOX Figure 14. USB Signals Min Max Unit 15 — — — ns — — ns symbolizes usb timing USIXKH USKHOX NVDD Ω USIXKH Freescale Semiconductor Notes for ...

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... TXn) within a differential pair. There is only one signal trace curve in a differential waveform. The voltage represented in the differential waveform is not referenced to ground. Refer to MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor (or Differential Output Swing) OD – V ...

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... which is the arithmetic mean of the two complimentary Differential Swing Differential Peak Voltage, V Differential Peak-Peak Voltage, V DIFFpp is 500 mV in one phase and –500 mV in the other 500 mV. The peak-to-peak differential voltage (V DIFFp – – B| DIFFp = 2*V (not shown) DIFFp Freescale Semiconductor ) DIFFp-p ...

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... AC-coupled off-chip. • The input amplitude requirement — This requirement is described in detail in the following sections. SD_REF_CLK SD_REF_CLK Figure 16. Receiver of SerDes Reference Clocks MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) Table 1 50 Ω Input Amp 50 Ω and Table 2 ...

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... AC-coupled into the unused phase (SD_REF_CLK) through the same source impedance as the clock input (SD_REF_CLK) in use. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Section 10.2.1, “SerDes Reference the maximum average current requirements sets the Figure 18 shows the SerDes reference clock input Figure 19 shows Freescale Semiconductor ...

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... LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor High-Speed Serial Interfaces (HSSI) Vmax < 80 0mV 100 mV < Vcm < 400 mV Vmin > ...

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... They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended ...

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... CLK_Out Clock Driver Clock Driver CLK_Out 10 nF Figure 21. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only) MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor SD_REF_CLK 100 Ω differential PWB trace SD_REF_CLK High-Speed Serial Interfaces (HSSI) MPC8308 50 Ω SerDes Refer. ...

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... CLK_Out R1 Clock Driver Clock Driver CLK_Out R1 Figure 22. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only) MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev SD_REF_CLK 10nF R2 100 Ω differential PWB trace SD_REF_CLK Figure 22 MPC8308 50 Ω SerDes Refer. CLK Receiver 50 Ω Freescale Semiconductor ...

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... Parameter Rising Edge Rate Falling Edge Rate Differential Input High Voltage Differential Input Low Voltage MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Total 50 Ω. Assume clock driver’s output impedance is about 16 Ω. SD_REF_CLK 100 Ω differential PWB trace SD_REF_CLK 50 Ω ...

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... For detailed information, see the following sections: • Section 11.2, “AC Requirements for PCI Express SerDes Clocks” MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Symbol Rise-Fall Matching 24). Figure 25). SD_REF_CLK SD_REF_CLK Min Max Unit Notes — Freescale Semiconductor ...

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... REFCLK cycle time (for 125 MHz and 100 MHz) REF t REFCLK cycle-to-cycle jitter. Difference in the period REFCJ of any two adjacent REFCLK cycles. t Phase jitter. Deviation in edge location with respect to REFPJ mean edge location. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Ω 50 Ω Min 8 — –50 PCI Express 50 Ω ...

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... UI. A recovered calculated over 3500 consecutive unit intervals of sample data. Jitter is measured using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. Typical Max Units Notes 400 400. — 1 –3.5 –4 — — — 0. Freescale Semiconductor ...

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... V TX-RCV-DETECT allowed during receiver detection TX DC common mode V TX-DC-CM voltage TX short circuit current I TX-SHORT limit Minimum time spent in T TX-IDLE-MIN electrical idle MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Comments Min , — 0.125 V = — PEACPCMTX RMS(| |/2 - TXD+ TXD TX-CM-DC ...

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... An external capacitor of 100nF is recommended. Typical Max Units Notes — — — — — — — — Ω 100 120 — Ω — — — — 500 + 2 ps — UI — 200 nF — Freescale Semiconductor ...

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... It is recommended that the recovered calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function (that is, least squares and median deviation fits). MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Comments Min This random timeout helps ...

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... V = 2*|V - PEDPPRX RX- RX-D- The maximum interconnect media and Transmitter jitter that can be tolerated by the Receiver can be derived RX-MAX-JITTER U = 0.6 UI. PEEWRX TX-DIFF (D+ D– Crossing Point) ) Min Typical Max Units 400 400.12 ps 0.175 — 1.200 V 0.4 — — UI Freescale Semiconductor Notes ...

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... V RX-IDLE-DET-DIF threshold Fp-p Unexpected Electrical Idle T RX-IDLE-DET-DIFF Enter Detect Threshold - Integration Time ENTERTIME MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Comments Min Jitter is defined as the — measurement variation of the crossing points ( PEDPPRX relation to a recovered TX UI. A recovered calculated over 3500 consecutive unit intervals of sample data ...

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... Figure 28) expected at the input receiver based on an Typical Max Units Notes — — Figure 29 should be used Figure 28). If the specification ensures a jitter distribution optional for the return TX Freescale Semiconductor ...

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... The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from D+ and D– not being exactly matched in length at the package pin boundary. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor NOTE Figure 29). Note that the series capacitors > ...

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... Input hold from local bus clock (Note revisited) MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Symbol – Symbol t LBK t LBIVKH t LBIXKH Min Max Unit 2 0.3 DD –0.3 0.8 μA — ±5 NV – 0.2 — DD — 0.2 Min Max Unit Notes 15 — — — Freescale Semiconductor ...

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... For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Figure 30 provides the AC test load for the local bus. Output MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor 1 Symbol t LBKHOV t ...

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... In what follows, T1, T2, T3, and T4 are internal clock reference phase signals corresponding to LCCR[CLKDIV]. LCLK0 Input Signals: LD[0:15] Input Signal: LGTA t Output Signals: LBCTL//LOE/ Output Signals: LA[0:25] Figure 31. Local Bus Signals, Non-Special Signals Only MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev LBIVKH LBKHOV t LBKHOZ t LBKHOV t LBIXKH t LBIVKH t LBIXKH t LBIXKH Freescale Semiconductor ...

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... GPCM Mode Output Signals: LCS[0:3]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LD[0:15] UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 32. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor t LBKHOZ t LBKHOV t LBIVKH t t LBKHOZ ...

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... Table 38. eSDHC interface DC Electrical Characteristics Characteristic Output high voltage Output low voltage MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev LBKHOZ t LBKHOV t LBIVKH t LBKHOZ t LBKHOV range is between 3.0 V and 3 Symbol Condition –8 8 LBIXKH t LBIXKH t LBIVKH Min Max Unit 2.4 — V — 0.5 V Freescale Semiconductor ...

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... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). 2 Measured at capacitive load of 40 pF. 3 For reference only, according to the SD card specifications. 4 Average, for reference only. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Symbol Condition 3 — ...

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... Input at the MPC8308 Pins MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev SFSCK VM = Midpoint Voltage ( (Clock Cycle) SFSCK Driving Edge t CLK_DELAY SFSKHOV SFSKHOX t DATA_DELAY t ISU Figure 35. Full Speed Output Path t t SFSCKL SFSCKH t t SFSCKF SFSCKR /2) Sampling Edge t SFSCKL ns) Freescale Semiconductor ...

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... Input setup times: SD_CMD, SD_DATx Input hold times: SD_CMD, SD_DATx Output delay time: SD_CLK to SD_CMD, SD_DATx valid Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid SD Card Input Setup SD Card Input Hold MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor t (Clock Cycle) SFSCK t CLK_DELAY Driving ...

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... V ± 300 mV. 1 Symbol t ODLY t OH (first three letters of functional block)(signal)(state) (reference)(state) for outputs. For example SHSCK VM = Midpoint Voltage (NVDD/2) Min Max Unit Notes — 2.5 — ns symbolizes eSDHC SFSIXKH SHSCK SHSCKH t t SHSCKF SHSCKR Freescale Semiconductor 3 3 ...

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... SD CLK at the MPC8308 Pin Driving SD CLK at the Card Pin Output from the SD Card Pins Input at the MPC8308 Pins MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor t (Clock Cycle) SHSCK Driving Edge t CLK_DELAY SHSKHOV t SHSKHOX ...

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... JTIXKH t JTKLDV TDO t JTKLOV Min Max Unit 2 0 –0.3 0.8 V μA ±5 2.4 — V — 0.5 V — 0.4 V Figure 41 through Figure 44. 1 Min Max Unit Notes 0 33.3 MHz 30 — — — — 4 — — 10 — Freescale Semiconductor — — — — ...

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... AC test load for TDO and the boundary-scan outputs. Output Figure 40. AC Test Load for the JTAG Interface Figure 41 provides the JTAG clock input timing diagram. JTAG External Clock Figure 41. JTAG Clock Input Timing Diagram MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Table 2). 2 Symbol t JTKLDX TDO t ...

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... TRST VM = Midpoint Voltage (NV DD Figure 42. TRST Timing Diagram VM t JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (NV DD Figure 43. Boundary-Scan Timing Diagram VM t JTIVKH t JTKLOV t JTKLOZ VM = Midpoint Voltage ( / JTDXKH Input Data Valid Output Data Valid / JTIXKH Input Data Valid Output Data Valid /2) Freescale Semiconductor ...

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... Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data hold time: Fall time of both SDA and SCL signals MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor 2 C interface. 2 Table 43 Electrical Characteristics of 3.3 V ± ...

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... I2C symbolizes I I2PVKH clock reference I2C of the SCL signal) to bridge the IHmin ) of the SCL signal. I2CL AC parameter. I2CF Ω I2KHKL I2CF t I2CR t I2PVKH P Freescale Semiconductor Max Unit μs — μs — — V — V for C timing (I2 timing S ...

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... Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any external synchronous logic. Timers inputs are required to be valid for at least t Figure 47 provides the AC test load for the Timers. Output MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Symbol Condition –8.0 mA ...

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... MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Table 47. GPIO DC Electrical Characteristic Symbol Condition – — — ≤ V ≤ Symbol t PIWID = 50 Ω Figure 48. GPIO AC Test Load Min Max Unit 2.4 — V — 0.5 V — 0 –0.3 0.8 V μA — ± Min Unit PIWID Ω Freescale Semiconductor ...

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... This section describes the DC and AC electrical specifications for the SPI of the device. 19.1 SPI DC Electrical Characteristics Table 51 provides the DC electrical characteristics for the MPC8308 SPI. Characteristic Input high voltage Input low voltage Input current MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Table 49. IPIC DC Electrical Characteristics Symbol Condition V — — — ...

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... V — 0 Symbol Min Max t — 6 NIKHOV t 0.5 — NIKHOX t 8.5 NEKHOV t 2 — NEKHOX t 6 — NIIVKH t 0 — NIIXKH t 4 — NEIVKH t 2 — NEIXKH symbolizes the internal NIKHOX Ω 52. Note that although the specifications Freescale Semiconductor Unit for ...

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... Package Parameters for the MPC8308 MAPBGA The package parameters are as provided in the following list. The package type × 19 mm, 473 MAPBGA. Package outline Interconnects Pitch Module height (typical) Solder Balls Ball diameter (typical) MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor t NEIXKH t NEKHOV t NIIXKH t NIIVKH t ...

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... Mechanical Dimensions of the MPC8308 MAPBGA Figure 52 shows the mechanical dimensions and bottom surface nomenclature of the MAPBGA package. Figure 52. Mechanical Dimension and Bottom Surface Nomenclature of the MPC8308 MAPBG Notes: 1. All dimensions are in millimeters. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Freescale Semiconductor ...

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... MEMC_MDQ[11] MEMC_MDQ[12] MEMC_MDQ[13] MEMC_MDQ[14] MEMC_MDQ[15] MEMC_MDQ[16] MEMC_MDQ[17] MEMC_MDQ[18] MEMC_MDQ[19] MEMC_MDQ[20] MEMC_MDQ[21] MEMC_MDQ[22] MEMC_MDQ[23] MEMC_MDQ[24] MEMC_MDQ[25] MEMC_MDQ[26] MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Table 53. MPC8308 Pinout Listing Package Pin Number DDR Memory Controller Interface V6 Y4 AB3 AA3 AA2 AA1 ...

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... AC3 I/O V1 I/O R1 I/O M1 I Freescale Semiconductor Power Notes Supply GV — DDB GV — DDB GV — DDB GV — DDB GV — DDB GV — DDA GV — DDA GV — DDB GV — DDB GV — DDB GV — DDA GV — DDA GV — DDB GV — DDB GV — DDB GV — ...

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... MEMC_MCK [2] MEMC_MODT[0] MEMC_MODT[1] MEMC_MECC[0] MEMC_MECC[1] MEMC_MECC[2] MEMC_MECC[3] MEMC_MECC[4] MEMC_MECC[5] MEMC_MECC[6] MEMC_MECC[7] MV REF LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Package Pin Number Local Bus Controller Interface U18 V18 ...

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... O AC16 O Y14 O AC15 O U13 O V13 O Y13 O AB15 O AA14 O AB14 O U12 O V12 O Y12 O AC14 O AA13 O AB13 O AA12 O Freescale Semiconductor Power Notes Supply NV 8 DDP_K NV 8 DDP_K NV 8 DDP_K NV 8 DDP_K NV 8 DDP_K NV — DDP_K NV — DDP_K NV — DDP_K NV — DDP_K NV — DDP_K NV — ...

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... UART_SOUT1/MSRCID0/LSRCID0 UART_SIN1/MSRCID1/LSRCID1 UART_SOUT2/MSRCID2/LSRCID2 UART_SIN2/MSRCID3/LSRCID3 TXA TXA RXA RXA SD_IMP_CAL_RX SD_REF_CLK SD_REF_CLK SD_PLL_TPD SD_IMP_CAL_TX SD_PLL_TPA_ANA SDAVDD_0 SDAVSS_0 IIC_SDA1 IIC_SCL1 MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Package Pin Number Pin Type Y11 O AB11 O AC11 O U11 O Y10 O AA10 O AB10 O AC10 O AB9 ...

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... NV 4 DDP_K DDP_K DDP_K DDP_K DDP_K NV 1 DDP_K I NV — DDP_K NV — DDP_K I NV — DDP_K I NV — DDJ O NV — DDP_K DDP_K I NV — DDC I NV — DDC DDC I NV — DDC I NV — DDC I NV — DDC Freescale Semiconductor ...

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... SD_DAT[1]/GTM1_TOUT2/GPIO[21] SD_DAT[2]/GTM1_TIN2/GPIO[22] SD_DAT[3]/GTM1_TGATE2/GPIO[23] SPIMOSI/MSRCID4/LSRCID4 SPIMISO/MDVAL/LDVAL SPICLK SPISEL GPIO[0]/TSEC2_COL GPIO[1]/TSEC2_TX_ER GPIO[2]/TSEC2_GTX_CLK GPIO[3]/TSEC2_RX_CLK MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Package Pin Number Pin Type C21 C20 D20 C23 E23 F22 I/O F21 I/O ...

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... I/O NV — DDH I/O NV — DDH I/O NV — DDH I/O NV — DDH O NV — DDH O NV — DDH O NV — DDH I NV — DDH O NV — DDH O NV — DDH I NV — DDH I NV — DDH O NV — DDG Freescale Semiconductor ...

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... TSEC1_TMR_RX_ESFD/GPIO[3] TSEC1_TMR_TX_ESFD/ GPIO[4] GTM1_TGATE3 GTM1_TIN4 GTM1_TGATE4/ GPIO[15] GTM1_TIN3 GPIO[5] GPIO[6] AV DD1 AV DD2 NC, No Connection V DD MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Package Pin Number L18 L21 L22 L23 M23 M22 M21 M18 M20 N23 N21 N20 N18 P23 ...

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... T1, T4, U7, Y3, AC1 D15, F10, F14 I A10, B15, D14, G13, I G14, H12 Power Notes Supply — — — — — — — — — — — — — — — — — — — — — — — — Freescale Semiconductor ...

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... ECC by default. To disable the ECC an external strong pull up resistor or a buffer released to high impedance is needed. 8. This pin has weak internal pull-down that is always enabled MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Package Pin Number Pin Type A14, B12, C13 ...

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... PCI Express Protocol Converter PCVTR Mux SerDes PHY Figure 53. MPC8308 Clock Subsystem e300 Core e300 PLL csb_clk MCK[0:2] DDR Clock MCK[0:2] Divider ddr_clk /2 lbc_clk /n Local LBC Bus Clock Memory Divider Device eTSEC1 TSEC1_RX_CLK TSEC1_TX_CLK/ TSEC1_GTX_CLK125 Freescale Semiconductor DDR Memory Device ...

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... DMA complex PCIEXP eSDHC USB The clock ratios of these units must be set before they are accessed. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Table 54 specifies which units have a configurable clock Table 54. Configurable Clock Units Default Frequency csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 ...

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... MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Maximum Operating Frequency Table 56 Table 56. System PLL Ratio csb_clk: SYS_CLK_IN Reserved Reserved Reserved the LBCM, DDRCM, and SPMF parameters in the reset Unit 400 MHz 133 MHz 133 MHz 66 MHz shows the multiplication factor Freescale Semiconductor ...

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... MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Table 57 shows the expected frequency values for the CSB frequency Table 57. CSB Frequency Options Input Clock Frequency (MHz) 25 2:1 4:1 5:1 125 shows the encodings for RCWL[COREPLL]. COREPLL values that are NOTE Table 58 ...

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... Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — — Natural Convection 2 VCO Divider (VCOD Symbol Value Unit R 42 °C/W θ °C/W θ °C/W θJMA R 24 °C/W θJMA R 17 °C/W θ °C/W θJC Ψ 2 °C/W JT Freescale Semiconductor Notes 1,2 1,2,3 1,3 1 ...

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... In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Board Type × I ...

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... System Design Information This section provides electrical and thermal design recommendations for successful application of the device MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Ψ ) can be used to determine the junction temperature with Freescale Semiconductor ...

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... Therefore recommended that the system designer place at least one decoupling capacitor at each V MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Section 21.2, “System PLL Configuration.” Section 21.3, “Core PLL Configuration.” level should always be equivalent to V ...

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... MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev planes, to enable quick recharging of the smaller chip capacitors MDIO and HRESET) is trimmed until the voltage at the pad equals P )/ required. Unused active high DD1 DD2 DD /2 (Figure 55). The output DD and R are designed to be close to each P N Freescale Semiconductor , and ...

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... I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor ...

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... MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev Table 61. Part Numbering Nomenclature Package 1 Frequency VM = Pb-free 473 AD = 266 MHz MAPBGA AF = 333 MHz AG = 400 MHz for more information on available package types e300 Core DDR Revision 3 Frequency Level D = 266 MHz Contact local Freescale sales office Freescale Semiconductor A ...

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... Parts are marked as in the example shown in Figure 56. Freescale Part Marking for PBGA Devices Table 62 shows the SVR settings. Device MPC8308 Note: PVR = 8085_0020 for the device. MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Figure 56. MPCnnnnCVMADDA core/platform MHZ ATWLYYWW CCCCC *MMMMM ...

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... MHz replaced with 400 MHz 105 replaced with T = 105 (Max replaced with 66.67 and t SYS_CLK_IN 53, TSEC1_TMR_RX_ESFD replaced with TSEC2_TMR_RX_ESFD 56, rows from 1000 to 1111 removed 57, SPMF 5:1 Option 167 MHz added. = 105° signal group DD (Min) = 15.15 replaced SYS_CLK_IN Freescale Semiconductor ...

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... THIS PAGE INTENTIONALLY LEFT BLANK MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2 Freescale Semiconductor Document Revision History 89 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...