IC MPU PWRQUICC II 516-PBGA

MPC8321VRADDC

Manufacturer Part NumberMPC8321VRADDC
DescriptionIC MPU PWRQUICC II 516-PBGA
ManufacturerFreescale Semiconductor
SeriesPowerQUICC II PRO
MPC8321VRADDC datasheet
 


Specifications of MPC8321VRADDC

Processor TypeMPC83xx PowerQUICC II Pro 32-BitSpeed266MHz
Voltage1VMounting TypeSurface Mount
Package / Case516-PBGAProcessor SeriesMPC8xxx
Coree300Data Bus Width32 bit
Development Tools By SupplierMPC8323E-MDS-PBMaximum Clock Frequency266 MHz
Maximum Operating Temperature+ 105 CMounting StyleSMD/SMT
I/o Voltage1.8 V, 2.5 V, 3.3 VMinimum Operating Temperature0 C
Core Size32 BitProgram Memory Size32KB
Cpu Speed266MHzEmbedded Interface TypeI2C, SPI, USB, UART
Digital Ic Case StyleBGANo. Of Pins516
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
Features-  
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Freescale Semiconductor
Technical Data
MPC8323E
PowerQUICC II Pro Integrated
Communications Processor
Family Hardware Specifications
This document provides an overview of the MPC8323E
PowerQUICC II Pro processor features. The MPC8323E is a
cost-effective, highly integrated communications processor
that addresses the requirements of several networking
applications, including ADSL SOHO and residential
gateways, modem/routers, industrial control, and test and
measurement applications. The MPC8323E extends current
PowerQUICC offerings, adding higher CPU performance,
additional functionality, and faster interfaces, while
addressing the requirements related to time-to-market, price,
power consumption, and board real estate. This document
describes the MPC8323E, and unless otherwise noted, the
information also applies to the MPC8323, MPC8321E, and
MPC8321.
To locate published errata or updates for this document, refer
to the MPC8323E product summary page on our website
listed on the back cover of this document or contact your
local Freescale sales office.
© 2010 Freescale Semiconductor, Inc. All rights reserved.
Document Number: MPC8323EEC
Rev. 4, 09/2010
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 9
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 11
6. DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . 13
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8. Ethernet and MII Management . . . . . . . . . . . . . . . . . 19
9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2
11. I
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
15. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
17. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
18. UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
19. HDLC, BISYNC, Transparent, and Synchronous
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
20. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
21. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 49
22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
24. System Design Information . . . . . . . . . . . . . . . . . . . 76
25. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 79
26. Document Revision History . . . . . . . . . . . . . . . . . . . 80

MPC8321VRADDC Summary of contents

  • Page 1

    ... To locate published errata or updates for this document, refer to the MPC8323E product summary page on our website listed on the back cover of this document or contact your local Freescale sales office. © 2010 Freescale Semiconductor, Inc. All rights reserved. Document Number: MPC8323EEC Rev. 4, 09/2010 Contents 1 ...

  • Page 2

    ... Virtual DMAs 1 UL2/8-Bit Figure 1. MPC8323E Block Diagram System Interface Unit (SIU) Memory Controllers GPCM/UPM DDR 32-Bit DDR1/DDR2 Interface Unit PCI PCI Controller Local Local Bus Bus Arbitration DUART Channel DMA Interrupt Controller Protection and Configuration System Reset Clock Synthesizer Freescale Semiconductor ...

  • Page 3

    ... IP termination support for IPv4 and IPv6 packets including TOS, TTL, and header checksum processing • Extensive support for ATM statistics and Ethernet RMON/MIB statistics • Support for 64 channels of HDLC/transparent MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor NOTE Overview 3 ...

  • Page 4

    ... Four independent 16-bit timers that can be interconnected as two 32-bit timers The UCCs are similar to the PowerQUICC II peripherals: SCC (BISYNC, UART, and HDLC bus) and FCC (fast Ethernet, HDLC, transparent, and ATM). MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev interface Freescale Semiconductor ...

  • Page 5

    ... The PIC programming model is compatible with the MPC8260 interrupt controller, and it supports 8 external and 35 internal discrete interrupt sources. Interrupts can also be redirected to an external interrupt controller. MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Overview 5 ...

  • Page 6

    ... V. This limit may be exceeded for a maximum of 100 ms during DD 1 Max Value Unit –0.3 to 1.26 V –0.3 to 1.26 V –0 –0.3 to 1.98 –0 –0.3 to ( –0.3 to ( –0.3 to ( –0.3 to ( °C –55 to 150 Freescale Semiconductor Notes — — — — — ...

  • Page 7

    ... G/ GND – 0 GND – 0.7 V Note refers to the clock period associated with the bus clock interface. interface Figure 2. Overshoot/Undershoot Voltage for GV MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol maximum temperature is specified with T A Section 24.2, “PLL Power Supply ...

  • Page 8

    ... Output Impedance (Ω Table 4. Input Capacitance Specification Symbol ICLKIN ) and IO supply voltages (GV DD Figure 3. Once both the power supplies (I/O voltage and core voltage) are Supply Voltage Min Max Unit Notes — pF and before the I/O DD Freescale Semiconductor — ...

  • Page 9

    ... MHz, 1 × 32 bits DDR I/O 65% utilization 2 Ω Ω pair of clocks MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor I/O Voltage (GV Core Voltage (V >= 32 clocks x t Table 5. MPC8323E Power Dissipation Core Typical Frequency (MHz) 266 0.74 333 0.78 ...

  • Page 10

    ... NOTE NOTE Condition Symbol — — 0.12 W — 0.057 W — 0.041 W Multiply by number of 0.001 W interfaces used. 0.004 W 0.003 W 0.025 W 0.017 W 0.009 W 0.009 W 0.002 W 0.001 W 0.001 W 0.002 W Min Max Unit 2 0 –0.3 0.4 V Freescale Semiconductor ...

  • Page 11

    ... Required assertion time of PORESET with stable clock applied to CLKIN when the MPC8323E is in PCI host mode Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN when the MPC8323E is in PCI agent mode MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor 0 V ≤ V ≤ ...

  • Page 12

    ... Max Unit 512 — t PCI_SYNC_IN 16 — t PCI_SYNC_IN 4 — t CLKIN 4 — t PCI_SYNC_IN 0 — ns — — t PCI_SYNC_IN Max Unit μs — 100 Min Max Unit 2.4 — V — 0.5 V — 0 –0.3 0.8 V Freescale Semiconductor Notes — Notes — Table 9. Notes — ...

  • Page 13

    ... Output leakage is measured with all outputs disabled Table 13 provides the DDR2 capacitance when Dn_GV Table 13. DDR2 SDRAM Capacitance for D n Parameter/Condition Input/output capacitance: DQ, DQS MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Condition 0 V ≤ V ≤ ...

  • Page 14

    ... GV (typ Max Unit 2.625 V 0.51 × MVREF n + 0.04 V REF 0 MVREF n – 0.15 V REF μA –9.9 — mA — variations as measured at the receiver REF . DD (typ) = 2.5 V Interface DD Min Max Unit — 0.5 pF ÷ OUT DD Freescale Semiconductor 1 Notes — — 4 — — Notes 1 1 ...

  • Page 15

    ... MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t determined by the following equation: t absolute value CISKEW MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor of 1.8 ± 5%. DD Symbol Min V — ...

  • Page 16

    ... MHz 3.5 t DDKHAX 266 MHz 2.5 200 MHz 3.5 t DDKHCS 266 MHz 2.5 200 MHz 3.5 t DDKHCX 266 MHz 2.5 200 MHz 3.5 t –0.6 DDKHMH t DISKEW Max Unit — — ns — — ns — — ns — — 0.6 ns Freescale Semiconductor Notes ...

  • Page 17

    ... The data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that t symbol conventions described in note 1. MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor of (1.8 or 2.5 V) ± 5 ...

  • Page 18

    ... MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev MCK MCK t MCK t (max) = 0.6 ns DDKHMH t (min) = –0.6 ns DDKHMH Figure 5. Timing Diagram for t t MCK t ,t DDKHAS DDKHCS t ,t DDKHAX DDKHCX NOOP t DDKHMH t DDKHDS t DDKLDS DDKLDX t DDKHDX DDKHMH DDKHMH t DDKHME Freescale Semiconductor ). ...

  • Page 19

    ... Ethernet Controller (10/100 Mbps)—MII/RMII Electrical Characteristics The electrical characteristics specified here apply to all MII (media independent interface) and RMII (reduced media independent interface), except MDIO (management data input/output) and MDC MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol ...

  • Page 20

    ... DD of 3.3 V ± 10 Symbol t MTX t MTX t /t MTXH MTX t MTKHDX t MTXR Table Min Max Unit 2.97 3.63 2. 0.3 DD GND 0.50 2 0.3 DD –0.3 0.90 — ±5 Min Typical Max Unit — 400 — — 40 — 35 — 1.0 — 4.0 Freescale Semiconductor 22 μ ...

  • Page 21

    ... RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise time MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor of 3.3 V ± 10 Symbol t MTXF (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...

  • Page 22

    ... Note that, in general, MRX = 50 Ω Figure 8. AC Test Load t MRX t t MRXH MRXF Valid Data t MRDVKH Figure 9. MII Receive AC Timing Diagram Min Typical Max 1.0 — 4.0 symbolizes MII receive MRDVKH clock reference (K) MRX Ω MRXR t MRDXKH Freescale Semiconductor Unit ns for ...

  • Page 23

    ... REF_CLK clock period REF_CLK duty cycle RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK REF_CLK clock rise V (min (max MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor of 3.3 V ± 10 Symbol t RMX t /t RMXH ...

  • Page 24

    ... Figure 11. AC Test Load t RMX t t RMXH RMXF Valid Data t RMRDVKH Figure 12. RMII Receive AC Timing Diagram Section 8.1, “Ethernet Controller (10/100 Mbps)—MII/RMII Electrical Min Typical Max 1.0 — 4.0 symbolizes RMII RMRDVKH RMX Ω RMXR t RMRDXKH Freescale Semiconductor Unit ns for clock ...

  • Page 25

    ... For rise and fall times, the latter MDC convention is used with the appropriate letter: R (rise (fall). MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Table 27. Symbol Conditions OV — ...

  • Page 26

    ... MDC t t MDCH MDCF t MDDVKH t MDDXKH t MDKHDX Symbol Symbol t LBK t LBIVKH t LBIXKH t LBOTOT1 t MDCR Min Max 0.3 DD –0.3 0.8 OV – 0.2 — DD — 0.2 — ±5 Min Max Unit 15 — — ns 1.0 — ns 1.5 — ns Freescale Semiconductor Unit μA Notes ...

  • Page 27

    ... For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Figure 14 provides the AC test load for the local bus. Output MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor 1 Symbol t LBOTOT2 t ...

  • Page 28

    ... UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 16. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev LBIVKH t LBKHOV t LBKHOZ t LBKHOV t LBOTOT t LBKHOZ t LBKHOV t LBIVKH t LBKHOZ t LBKHOV t LBIXKH t LBIVKH t LBIXKH t LBIXKH t LBIXKH t LBIXKH t LBIVKH Freescale Semiconductor ...

  • Page 29

    ... DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the MPC8323E. Table 31. JTAG Interface DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage Input high voltage MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor t LBKHOZ t LBKHOV t LBIVKH t t ...

  • Page 30

    ... JTDXKH TMS, TDI t JTIXKH t JTKLDV TDO t JTKLOV t JTKLDX TDO t JTKLOX Min Max –0.3 0.8 — ±5 DD Figure 19 through 1 Min Max Unit 0 33.3 MHz 30 — — — — 4 — — 10 — — 2 — Freescale Semiconductor Unit V μA Notes — — — — ...

  • Page 31

    ... Figure 19 provides the JTAG clock input timing diagram. JTAG External Clock Figure 19. JTAG Clock Input Timing Diagram Figure 20 provides the TRST timing diagram. TRST MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Table 2). 2 Symbol t JTKLDZ TDO t ...

  • Page 32

    ... MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (OV DD /2) Figure 21. Boundary-Scan Timing Diagram VM t JTIVKH t JTKLOV t JTKLOZ VM = Midpoint Voltage ( JTDXKH Input Data Valid Output Data Valid VM t JTIXKH Input Data Valid Output Data Valid Freescale Semiconductor ...

  • Page 33

    ... Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data hold time: MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor 2 C interface of the MPC8323E. 2 Table 33 Electrical Characteristics of 3.3 V ± ...

  • Page 34

    ... OV — DD 0.2 × OV — symbolizes I C timing (I2) I2DVKH clock reference (K) going to the high I2C symbolizes I I2PVKH (min) of the SCL signal) to bridge the SCL signal. I2CL Ω I2CF t I2CR t I2PVKH P S Freescale Semiconductor Unit ns ns μs μ for 2 C clock I2C ...

  • Page 35

    ... For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Test Condition ≥ V ...

  • Page 36

    ... For example, t symbolizes PCI timing (PC) with respect to the time hard reset PCRHFV = 50 Ω Ω Figure 25. PCI AC Test Load t PCIVKH t PCIXKH Max Unit Notes — — — for symbolizes PCI timing PCIVKH , reference SYS Freescale Semiconductor ...

  • Page 37

    ... Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by any external synchronous logic. Timer inputs are required to be valid for at least t MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor t PCKHOV t ...

  • Page 38

    ... Figure 28. Timers AC Test Load Symbol Condition – — — ≤ V ≤ Ω Min Max Unit 2.4 — V — 0.5 V — 0 –0.3 0.8 V μA — ± Symbol Min t 20 PIWID ns to ensure proper operation. PIWID Freescale Semiconductor Notes — — Unit ns ...

  • Page 39

    ... IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any external synchronous logic. IPIC inputs are required to be valid for at least t in edge triggered mode. MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor = 50 Ω Ω ...

  • Page 40

    ... Figure 30. SPI AC Test Load Min Max 2.4 — — 0.5 — 0.4 2 0.3 DD –0.3 0.8 — ± Min Max 0.5 6 NIKHOV — NIIVKH t 0 — NIIXKH 4 — NEIVKH 2 — NEIXKH symbolizes the NMSI NIKHOV Ω Freescale Semiconductor Unit μA Unit for ...

  • Page 41

    ... DC electrical characteristics for the MPC8323E TDM/SI. Table 46. TDM/SI DC Electrical Characteristics Characteristic Output high voltage Output low voltage Input high voltage MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Table 45. Note that although the specifications t NEIXKH t NEKHOV ...

  • Page 42

    ... TDM/ Ω Ω Figure 33. TDM/SI AC Test Load Table 47. Note that although the specifications generally t SEIXKH t SEKHOV t SEKHOX Min Max Unit –0.3 0.8 — ± Min Max Unit — 2 — symbolizes the TDM/SI SEKHOX Freescale Semiconductor V μ for ...

  • Page 43

    ... The symbols used for timing specifications follow the pattern of t inputs and t (first two letters of functional block)(reference)(state)(signal)(state) outputs internal timing (UI) for the time t invalid (X). MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor NOTE Symbol Condition – ...

  • Page 44

    ... UTOPIA Output Signals: UTOPIA Figure 37. UTOPIA AC Timing (Internal Clock) Diagram MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Ω Figure 35. UTOPIA AC Test Load Table 49. Note that although the specifications t UEIXKH t UEKHOV t UEKHOX t UIIXKH t UIIVKH t UIKHOV t UIKHOX Ω Freescale Semiconductor ...

  • Page 45

    ... Outputs—External clock high impedance Inputs—Internal clock input setup time Inputs—External clock input setup time Inputs—Internal clock input hold time MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor HDLC, BISYNC, Transparent, and Synchronous UART Symbol Condition – ...

  • Page 46

    ... Figure 38. AC Test Load Table 51. Note that although the specifications 1 (continued) 2 Min Max 1 — symbolizes the outputs HIKHOX 1 2 Min Max — 4 — 0 — 1 — symbolizes the outputs UAIKHOX Ω L Freescale Semiconductor Unit ns for Unit for ...

  • Page 47

    ... Serial CLK (Output) Input Signals: (See Note) Output Signals: (See Note) Note: The clock edge is selectable. Figure 40. AC Timing (Internal Clock) Diagram MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor HDLC, BISYNC, Transparent, and Synchronous UART t HEIXKH t HEKHOV t HEKHOX ...

  • Page 48

    ... Max Unit Notes — ns Full speed 48 MHz — ns Low speed 6 MHz 5 ns — Full speed transitions 100 ns Low speed transitions for receive signals symbolizes USB timing (US) for the USRSPND symbolizes USB timing (US) for the USB USTSPN Ω Freescale Semiconductor Unit μA ...

  • Page 49

    ... Mechanical Dimensions of the MPC8323E PBGA Figure 42 shows the mechanical dimensions and bottom surface nomenclature of the MPC8323E, 516-PBGA package. MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Section 21.1, “Package Parameters for the 27 mm × 516 1. Sn/36 Pb/2 Ag (ZQ package) 95 ...

  • Page 50

    ... ASME Y14.5M-1994. 3.Maximum solder ball diameter measured parallel to datum A. 4.Datum A, the seating plane, is determined by the spherical crowns of the solder balls. Figure 42. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8323E PBGA MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Freescale Semiconductor ...

  • Page 51

    ... MEMC_MDQ19 MEMC_MDQ20 MEMC_MDQ21 MEMC_MDQ22 MEMC_MDQ23 MEMC_MDQ24 MEMC_MDQ25 MEMC_MDQ26 MEMC_MDQ27 MEMC_MDQ28 MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Table 55. MPC8323E PBGA Pinout Listing Package Pin Number DDR Memory Controller Interface AE9 AD10 AF10 AF9 AF7 AE10 AD9 ...

  • Page 52

    ... AC17 O AE11 O AD11 O AC11 O Power Notes Supply GV — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — DD Freescale Semiconductor ...

  • Page 53

    ... LAD15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LCS0 MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number AD14 AF14 AE14 AF11 Local Bus Controller Interface N25 P26 P25 R26 R25 T26 ...

  • Page 54

    ... V24 L23 K23 J23 H23 G23 AC22 Y24 Y25 DUART interface AE24 AF24 Programmable Interrupt Controller AD25 AD26 K1 K2 Power Pin Type Notes Supply — — — — — — — — — — — — — — — DD Freescale Semiconductor ...

  • Page 55

    ... QUIESCE HRESET PORESET SRESET CLKIN CLKIN PCI_SYNC_OUT RTC_PIT_CLOCK PCI_SYNC_IN/PCI_CLK PCI_CLK0/clkpd_cerisc1_ipg_clkout/DPTC_OSC PCI_CLK1/clkpd_half_cemb4ucc1_ipg_clkout/ CLOCK_XLB_CLOCK_OUT PCI_CLK2/clkpd_third_cesog_ipg_clkout/ cecl_ipg_ce_clock MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number Pin Type J2 J1 AE26 AE25 AF25 F1 M23 JTAG W26 Y26 AA26 AB26 ...

  • Page 56

    ... AB1 Power Pin Type Notes Supply — — — — DDR — reference voltage I DDR — reference voltage — — — — — — — — — — — — — — — — — — — — — DD Freescale Semiconductor ...

  • Page 57

    ... PCI_C_BE3 PCI_PAR PCI_FRAME PCI_TRDY PCI_IRDY PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_SERR PCI_PERR PCI_REQ0 PCI_REQ1/CPCI_HS_ES PCI_REQ2 PCI_GNT0 PCI_GNT1/CPCI_HS_LED PCI_GNT2/CPCI_HS_ENUM M66EN MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number Pin Type AB2 AC1 IO AA3 IO AA4 IO AD1 IO AD2 IO AB3 ...

  • Page 58

    ... K24 IO K26 IO G25 IO G26 IO H25 IO H26 IO C25 IO C26 IO D25 IO D26 IO Power Notes Supply OV — — — — — — — — — — — — — — — — — — — — — — — — — — DD Freescale Semiconductor ...

  • Page 59

    ... GPIO_PB7/Enet3_RXD[3]/SER3_RXD[3]/ TDMC_RXD[3] GPIO_PB8/Enet3_RX_ER/SER3_CD/TDMC_REQ GPIO_PB9/Enet3_TX_ER/TDMC_CLKO GPIO_PB10/Enet3_RX_DV/SER3_CTS/ TDMC_RSYNC GPIO_PB11/Enet3_COL/RXD[4]/SER3_RXD[4]/ TDMC_STROBE GPIO_PB12/Enet3_TX_EN/SER3_RTS/ TDMC_TSYNC GPIO_PB13/Enet3_CRS/SDET GPIO_PB14/CLK12 GPIO_PB15 UPC1_TxADDR[4] GPIO_PB16 UPC1_RxADDR[4] MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number Pin Type E26 IO F25 IO E25 IO J25 IO F26 IO J26 IO ...

  • Page 60

    ... C7 IO A18 IO A19 IO B18 IO B19 IO A24 IO B24 IO A23 IO B26 IO A21 IO B20 IO Power Notes Supply OV — — — — — — — — — — — — — — — — — — — — — — — — — DD Freescale Semiconductor ...

  • Page 61

    ... GPIO_PC26/UPC1_RxPRTY/CE_EXT_REQ2 GPIO_PC27/UPC1_RxEN GPIO_PC28/UPC1_TxSOC GPIO_PC29/UPC1_TxCLAV/SER5_CTS GPIO_PC30/UPC1_TxPRTY GPIO_PC31/UPC1_TxEN/SER5_RTS GPIO_PD0/SPIMOSI GPIO_PD1/SPIMISO GPIO_PD2/SPICLK GPIO_PD3/SPISEL GPIO_PD4/SPI_MDIO/CE_MUX_MDIO GPIO_PD5/SPI_MDC/CE_MUX_MDC GPIO_PD6/CLK8/BRGO16/CE_EXT_REQ3 GPIO_PD7/GTM1_TIN1/GTM2_TIN2/CLK5 GPIO_PD8/GTM1_TGATE1/GTM2_TGATE2/CLK6 GPIO_PD9/GTM1_TOUT1 MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number Pin Type B21 IO A20 IO D19 IO C18 IO D18 IO A25 IO C21 IO D22 ...

  • Page 62

    ... P23, R5, R23, T5, T21, T22, U6, U22, V5, V22, W22, Y5, AB5, AB6, AC5 Power Pin Type Notes Supply IO OV — — — — — — — — — — — — — — — — — — — — — — — — — — DD Freescale Semiconductor ...

  • Page 63

    ... This pin must always be tied to GND. 7.This pin has weak internal pull-down N-FET that is always enabled.8.Though this pin has weak internal pull-up yet it is recommended to apply an external pull-up. MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number Pin Type ...

  • Page 64

    ... System PLL to local bus csb_clk to rest of the device PCI Clock Divider (÷2) Figure 43. MPC8323E Clock Subsystem core_clk DDR MEMC_MCK Clock Divider MEMC_MCK /2 /n Local Bus Memory LBC Device Clock LCLK[0:1] Divider PCI_CLK/ PCI_SYNC_IN 1 PCI_SYNC_OUT 0 3 PCI_CLK_OUT[0:2] Freescale Semiconductor DDR Memory Device ...

  • Page 65

    ... SPMF and COREPLL fields in the reset configuration word low (RCWL) which is loaded at power-on reset or by one of the hard-coded reset options. See the “Reset Configuration” section in the MPC8323E PowerQUICC II Pro Communications Processor Reference Manual for more information. MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Clocking 65 ...

  • Page 66

    ... MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Table 56 specifies which units have a configurable clock Table 56. Configurable Clock Units Default Frequency csb_clk Off, csb_clk /2, csb_clk /3 csb_clk Off, csb_clk NOTE Table 57. Operating Frequencies for PBGA 1 Options Max Operating Frequency Unit 333 MHz 133 MHz 200 MHz Freescale Semiconductor ...

  • Page 67

    ... CFG_CLKIN_DIV configuration input signal select the ratio between the primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor 1 2 NOTE Table 58 ...

  • Page 68

    ... Freescale Semiconductor ...

  • Page 69

    ... VCO divider (RCWL[COREPLL[0:1]]) must be set properly so that the core VCO frequency is in the range of 500–800 MHz. MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor shows the encodings for RCWL[COREPLL]. COREPLL values not listed Table 60. e300 Core PLL Configuration ...

  • Page 70

    ... MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev QUICC Engine PLL Multiplication RCWL[CEPDF] Factor = RCWL[CEPMF RCWL[CEPDF Table 62. QUICC Engine PLL VCO Divider RCWL[CEVCOD] VCO Divider Reserved NOTE Reserved × 2 × 3 × 4 × 5 × 6 × 7 × 8 Reserved Table Freescale Semiconductor Table 61 62. ...

  • Page 71

    ... Table 64. Package Thermal Characteristics for PBGA Characteristic Junction-to-ambient natural convection Junction-to-ambient natural convection Junction-to-ambient (@200 ft/min) Junction-to-ambient (@200 ft/min) Junction-to-board Junction-to-case MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Table 63. Suggested PLL Configurations Input Clock CEMF CEDF Frequency (MHz) 0110 0 33 ...

  • Page 72

    ... MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Board type Natural convection × where P is the power dissipation of the I/O drivers I/O I/O , can be obtained from the equation Symbol Value Unit Ψ 2 °C/W JT – are possible Freescale Semiconductor Notes 6 ...

  • Page 73

    ... When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case to ambient thermal resistance θ θ θ MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor ) D ) can be used to determine the junction temperature with Thermal 73 ...

  • Page 74

    ... Internet: www.mei-thermal.com Tyco Electronics Chip Coolers™ P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev For instance, the user can change the size of the heat θ CA 603-224-9988 408-567-8082 408-436-8770 800-522-2800 Freescale Semiconductor ...

  • Page 75

    ... MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor 603-635-5102 781-935-4850 800-248-2481 ...

  • Page 76

    ... The frequency ) DD Section 22.5, “Core PLL Configuration.” 1 which uses the same reference as the system PLL. The QUICC ) DD , and preferably these voltages are derived DD Figure 44, one to each of the five AV DD Freescale Semiconductor pins. By ...

  • Page 77

    ... GND. Then, the value of each resistor is varied until the pad voltage is OV MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor 2.2 µF 2.2 µF Low ESL Surface Mount Capacitors (<0.5 nH) GND Figure 44 ...

  • Page 78

    ... Solving for the output impedance gives source = V /R source 1 source Table 65. Impedance Characteristics PCI 25 Target 25 Target NA NA Table 105°C. j and R are designed to be close to each SW2 SW1 . Second, the output voltage is measured . The term source . DDR DRAM Symbol 20 Target Target DIFF Freescale Semiconductor = , DD Unit ...

  • Page 79

    ... Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other maximum core frequencies. MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Table 66. Part Numbering Nomenclature VR AF ...

  • Page 80

    ... Table 2. A Table 2. Section 4, “Clock Input Timing for rise/fall time of QE input pins. 43. Section 22.3, “System Clock Section 22.4, “System PLL Configuration. Table 55. Table 55. 3 .” Table 55, ”MPC8323E PBGA Pinout Specification. Table 8. Modified min value MCK Domains. Freescale Semiconductor Table 19. ...

  • Page 81

    ... Modified Section 2.2, “Power 1 6/2007 Correction to descriptive text in Section 2.2. 0 6/2007 Initial release. MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4 Freescale Semiconductor Table 67. Document Revision History Substantive Change(s) Table Table 6 DDR input timing diagram. Table Table 30 Table 2 stating junction temperature range 105• ...

  • Page 82

    ... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...