MPC8321VRADDC Freescale Semiconductor, MPC8321VRADDC Datasheet - Page 12

• Manufacturer Part Number: MPC8321VRADDC
• Description: IC MPU PWRQUICC II 516-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8321VRADDC

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8323E-MDS-PB
• Maximum Clock Frequency: 266 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 266MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 516
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Output high voltage
Output low voltage
Output low voltage
Input high voltage
Input low voltage
RESET Initialization
Table 10
5.1
Table 11
12
HRESET/SRESET assertion (output)
HRESET negation to SRESET negation (output)
Input setup time for POR configuration signals
(CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to
negation of PORESET when the MPC8323E is in PCI host mode
Input setup time for POR configuration signals
(CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to
negation of PORESET when the MPC8323E is in PCI agent mode
Input hold time for POR config signals with respect to negation of
HRESET
Time for the MPC8323E to turn off POR configuration signals with respect
to the assertion of HRESET
Time for the MPC8323E to turn on POR configuration signals with respect
to the negation of HRESET
Notes:
1. t
2. t
3. POR configuration signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
PLL lock times
primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the
MPC8323E PowerQUICC II Pro Integrated Communications Processor Reference Manual for more details.
the MPC8323E PowerQUICC II Pro Integrated Communications Processor Reference Manual for more details.
PCI_SYNC_IN
CLKIN
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
is the clock period of the input clock applied to CLKIN. It is only valid when the MPC8323E is in PCI host mode. See
provides the DC electrical characteristics for the MPC8323E reset signals mentioned in
provides the PLL lock times.
Characteristic
Reset Signals DC Electrical Characteristics
is the clock period of the input clock applied to PCI_SYNC_IN. When the MPC8323E is In PCI host mode the
Parameter/Condition
Parameter/Condition
Table 9. RESET Initialization Timing Specifications (continued)
Table 11. Reset Signals DC Electrical Characteristics
Symbol
V
V
V
V
V
OH
OL
OL
IH
IL
Table 10. PLL Lock Times
I
OH
I
I
OL
OL
Condition
= –6.0 mA
= 3.2 mA
= 6.0 mA
—
—
Min
—
Min
512
16
–0.3
—
Min
4
4
0
1
2.4
2.0
—
—
Max
OV
—
—
—
—
—
—
4
Max
100
DD
Max
0.5
0.4
0.8
—
+ 0.3
Freescale Semiconductor
t
t
t
t
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
PCI_SYNC_IN
t
CLKIN
Unit
ns
ns
Unit
Unit
μs
V
V
V
V
V
Table
Notes
Notes
Notes
1, 3
—
—
1
1
2
1
3
—
1
1
1
1
9.