MPC8321VRADDC Freescale Semiconductor, MPC8321VRADDC Datasheet - Page 17

• Manufacturer Part Number: MPC8321VRADDC
• Description: IC MPU PWRQUICC II 516-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8321VRADDC

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8323E-MDS-PB
• Maximum Clock Frequency: 266 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 266MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 516
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
At recommended operating conditions with D n _GV
MDQ/MDM output setup with respect to MDQS
MDQ/MDM output hold with respect to MDQS
MDQS preamble start
MDQS epilogue end
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MDM/MDQS. For the ADDR/CMD
4. Note that t
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), or data
6. All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that t
inputs and t
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
(A) are setup (S) or output valid time. Also, t
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by 1/2 applied
cycle.
from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t
of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the MPC8323E PowerQUICC II Pro Integrated Communications Processor Reference Manual for a
description and understanding of the timing modifications enabled by use of these bits.
mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
symbol conventions described in note 1.
DDKHAS
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
symbolizes DDR timing (DD) for the time t
DDKHMH
(first two letters of functional block)(reference)(state)(signal)(state)
Table 19. DDR1 and DDR2 SDRAM Output AC Timing Specifications (continued)
Parameter
follows the symbol conventions described in note 1. For example, t
266 MHz
200 MHz
266 MHz
200 MHz
DD
DDKLDX
of (1.8 or 2.5 V) ± 5%.
MCK
Symbol
t
t
t
t
t
t
DDKHDS,
DDKHDX,
DDKHMP
DDKHME
DDKLDS
DDKLDX
symbolizes DDR timing (DD) for the time t
memory clock reference (K) goes from the high (H) state until outputs
1
–0.5 × t
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. Output hold time can be read as DDR timing
1100
1200
–0.6
Min
0.9
1.0
MCK
– 0.6
DDKHMH
–0.5 × t
DDKHMH
Max
0.6
—
—
—
—
MCK
can be modified through control
describes the DDR timing (DD)
MCK
+ 0.6
memory clock reference
DDKHMP
DDR1 and DDR2 SDRAM
Unit
ns
ps
ns
ns
follows the
Notes
for
5
5
6
6
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