MPC8321VRADDC Freescale Semiconductor, MPC8321VRADDC Datasheet - Page 34

• Manufacturer Part Number: MPC8321VRADDC
• Description: IC MPU PWRQUICC II 516-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8321VRADDC

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8323E-MDS-PB
• Maximum Clock Frequency: 266 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 266MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 516
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

I
Figure 23
Figure 24
34
All values refer to V
2
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device (including
hysteresis)
Noise margin at the HIGH level for each connected device (including
hysteresis)
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. MPC8323E provides a hold time of at least 300 ns for the SDA signal (referred to the V
3. The maximum t
4. C
C
inputs and t
with respect to the time data input signals (D) reach the valid state (V) relative to the t
(H) state or setup time. Also, t
(S) went invalid (X) relative to the t
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
the undefined region of the falling edge of SCL.
B
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
SDA
SCL
= capacitance of one bus line in pF.
provides the AC test load for the I
shows the AC timing diagram for the I
S
(first two letters of functional block)(reference)(state)(signal)(state)
IH
I2DVKH
(min) and V
t
I2CF
t
I2CL
t
I2SXKL
has only to be met if the device does not stretch the LOW period (t
Output
Parameter
IL
Table 34. I
(max) levels (see
I2SXKL
I2C
symbolizes I
clock reference (K) going to the low (L) state or hold time. Also, t
Figure 24. I
t
I2DXKL
2
C AC Electrical Specifications (continued)
Figure 23. I
Table
t
Z
I2DVKH
0
2
= 50 Ω
t
33).
C timing (I2) for the time that the data with respect to the start condition
I2CH
2
2
C.
C Bus AC Timing Diagram
t
2
I2SXKL
2
C bus.
C AC Test Load
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
Sr
Symbol
t
t
t
I2PVKH
I2SVKH
I2KHDX
t
t
V
V
I2CR
I2CF
t
R
I2KHKL
NH
NL
L
= 50 Ω
1
20 + 0.1 C
20 + 0.1 C
0.1 × OV
0.2 × OV
I2C
t
Min
IH
0.6
1.3
clock reference (K) going to the high
I2PVKH
OV
(min) of the SCL signal) to bridge
I2CL
I2DVKH
DD
DD
DD
t
I2CR
b
b
) of the SCL signal.
/2
4
4
symbolizes I
Freescale Semiconductor
I2PVKH
P
Max
300
300
—
—
—
—
t
I2CF
symbolizes I
2
C timing (I2)
S
I2C
Unit
ns
ns
μs
μs
clock
for
V
V
2
C