MPC8321VRADDC Freescale Semiconductor, MPC8321VRADDC Datasheet - Page 77

• Manufacturer Part Number: MPC8321VRADDC
• Description: IC MPU PWRQUICC II 516-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8321VRADDC

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 266MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8323E-MDS-PB
• Maximum Clock Frequency: 266 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 266MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 516
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Each circuit should be placed as close as possible to the specific AV
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of package, without the inductance of vias.
Figure 44
24.3
Due to large address and data buses, and high operating frequencies, the MPC8323E can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8323E system, and the
MPC8323E itself requires a clean, tightly regulated source of power. Therefore, it is recommended that
the system designer place at least one decoupling capacitor at each V
MPC8323E. These decoupling capacitors should receive their power from separate V
and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be
placed directly under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick
response time necessary. They should also be connected to the power and ground planes through two vias
to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo OSCON).
24.4
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OV
should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V
MPC8323E.
24.5
The MPC8323E drivers are characterized over process, voltage, and temperature. For all buses, the driver
is a push-pull single-ended driver type (open drain for I
To measure Z
or GND. Then, the value of each resistor is varied until the pad voltage is OV
Freescale Semiconductor
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
Connection Recommendations
Decoupling Recommendations
Output Buffer DC Impedance
shows the PLL power supply filter circuit.
DD
0
for the single-ended drivers, an external resistor is connected from the chip pad to OV
, OV
V
DD
DD
, and GV
10 Ω
Figure 44. PLL Power Supply Filter Circuit
DD
planes, to enable quick recharging of the smaller chip capacitors.
2.2 µF
GND
Low ESL Surface Mount Capacitors (<0.5 nH)
DD
2.2 µF
, or GV
2
C).
DD
DD
AV
, GV
as required. Unused active high inputs
DD
DD
DD
(or L2AV
DD
pin being supplied to minimize
, OV
, OV
DD
DD
DD
DD
)
, and GV
/2 (see
, and GND pins of the
System Design Information
DD
Figure
, OV
DD
pins of the
DD
45). The
, GV
DD
DD
DD
77
,