MPC852TCVR100A Freescale Semiconductor, MPC852TCVR100A Datasheet

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... To locate published errata or updates for this document, refer to the MPC852T product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office. © Freescale Semiconductor, Inc., 2004, 2007. All rights reserved. Document Number: MPC852TEC Rev. 4, 09/2007 Contents 1 ...

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... Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) • 32 address lines • Memory controller (eight banks) — Contains complete dynamic RAM (DRAM) controller — Each bank can be a chip select or RAS to support a DRAM bank MPC852T PowerQUICC™ Hardware Specifications, Rev Freescale Semiconductor ...

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... Supports continuous mode transmission and reception on all serial channels — 8-Kbytes of dual-port RAM — Eight serial DMA (SDMA) channels — Three parallel I/O registers with open-drain capability MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor GRACEFUL STOP TRANSMIT ) Features , ENTER HUNT ...

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... Normal high and normal low power modes to conserve power • 1.8 V core and 3.3-V I/O operation with 5-V TTL compatibility. Refer to the 5-V tolerant pins. Figure 1 shows the MPC852T block diagram. MPC852T PowerQUICC™ Hardware Specifications, Rev Table 5 for a listing of Freescale Semiconductor ...

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... Core Bus Fast Ethernet Controller DMAs FIFOs 10/100 Base-T 2 Baud Rate Media Access Control MII MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 4-Kbyte Instruction Cache Unified Instruction MMU Bus 32-Entry ITLB 4-Kbyte Data Cache Data MMU 32-Entry DTLB 2 Interrupt Parallel I/O ...

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... T stg + 20 DDL GND Not to Exceed 10 interface Value – 0.3 to 3.4 – 0 – 0.3 to 3.4 100 DDSYN GND – 0 DDH – +150 Table 5. Absolute maximum ratings are . This restriction applies to power-up and DDH 1 and V DDH DDL Freescale Semiconductor Table 1 Unit °C ...

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... Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2 MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 2. Operating Temperatures . Maximum temperatures are guaranteed as junction A Table 3. MPC852T Thermal Resistance Data ...

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... Table 5. DC Electrical Specifications Symbol V DDH V DDL V DDSYN Difference between DDL DDSYN IHC ) Maximum Unit 140 mW 180 mW 160 mW 200 mW 250 3.465 V. DDH Min Max 3.135 3.465 1.7 1.9 1.7 1.9 — 100 2.0 3.465 GND 0.8 0.7 × DDH DDH Freescale Semiconductor Unit ...

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... UPWAITA/GPL_A4, GPL_A5, ALE_A, CE1_A, CE2_A, DSCK, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, and BADDR(28:30) 7 Thermal Calculation and Measurement For the following discussions, P drivers. The V 7.1 Estimation with Junction-to-Ambient Thermal Resistance An estimation of the chip junction temperature, T × +(R θ MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol 3.0 V VOH DDH VOL = (V x IDDL where P ...

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... +(R θ where junction-to-board thermal resistance (ºC/W) θ board temperature (º power dissipation in package D MPC852T PowerQUICC™ Hardware Specifications, Rev – are possible θCA . For instance, the user can change the airflow around θ Freescale Semiconductor ...

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... Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54 Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220. MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor ) can be used to determine the junction temperature with ...

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... HRESET assertion, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after reset. MPC852T PowerQUICC™ Hardware Specifications, Rev that operates at a lower voltage than the I/O voltage V DDSYN during power-on reset or power down. DDH must not exceed 3.465. DDH V DDH MUR420 1N5820 and V (GND). DDH SS V DDL Freescale Semiconductor . DDH ...

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... Special care should be taken to minimize the noise levels on the PLL supply pins. For more information, please refer to the MPC866 PowerQUICC™ Family Reference Manual, Section 14.4.3, “Clock Synthesizer Power ( DDSYN MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor in the boot code after the reset deasserts. HRCW[DBGC] SIUMCR[DBGC] MBMR[GPLB4DIS} PAPAR[4–7] PAPAR[12– ...

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... Min Max Min MHz 66 MHz Max Min Max Min Max — — — — — +2 –2 +2 – — 1 — 1 0.50 — 0.50 — 0.50 4 — 4 — — 5 — 5 15.0 8.0 12.0 6.1 9.1 Freescale Semiconductor Max 66.67 66.67 Max 100 50 Unit ...

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... CLKOUT to TA, BI High-Z (when driven by the memory controller or PCMCIA interface) (MIN = 0.00 × 2.5) B14 CLKOUT to TEA assertion (MAX = 0.00 × 9.00) MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 9. Bus Operation Timings (continued) 33 MHz 40 MHz Min Max Min 12.1 18 ...

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... Freescale Semiconductor Unit ...

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... B1 – 2.00) B29a WE(0:3)/BS_B[0:3] negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 0, CSNT = 1, EBDF = 0 (MIN = 0.50 × B1 – 2.00) MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 9. Bus Operation Timings (continued) 33 MHz 40 MHz Min Max Min 13.20 — ...

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... Freescale Semiconductor Unit ...

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... B1 + 6.6) B32 CLKOUT falling edge to BS valid- as requested by control bit BST4 in the corresponding word in the UPM (MAX = 0.00 × 6.00) MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 9. Bus Operation Timings (continued) 33 MHz 40 MHz Min Max Min 43.50 — ...

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... Freescale Semiconductor Unit ...

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... B38 are specified to enable the freeze of the UPM output signals as described in 11 The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified in Figure 22. MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 9. Bus Operation Timings (continued) 33 MHz 40 MHz Min Max Min 20.70 — ...

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... Maximum output delay specification. B Minimum output hold time. C Minimum input setup time specification. D Minimum input hold time specification. Figure 5 provides the timing for the external clock. CLKOUT MPC852T PowerQUICC™ Hardware Specifications, Rev Figure 4. Control Timing Figure 5. External Clock Timing D B2 Freescale Semiconductor ...

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... Figure 7 provides the timing for the synchronous active pull-up and open-drain output signals. CLKOUT TS, BB TA, BI TEA Figure 7. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B8 B9 B8a B9 B8b B11 B12 B11a ...

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... It also applies to normal read accesses under the control of the UPM in the memory controller. CLKOUT TA D[0:31], DP[0:3] MPC852T PowerQUICC™ Hardware Specifications, Rev B16 B16a B16b B16 B17 B18 B19 Figure 9. Input Data Timing in Normal Case B17 B17a B17 Freescale Semiconductor ...

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... GPCM factors control. CLKOUT TS A[0:31] CSx OE WE[0:3] D[0:31], DP[0:3] Figure 11. External Bus Read Timing (GPCM Controlled—ACS = 00) MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B20 B21 B11 B12 B8 B22 B25 B28 B18 Bus Signal Timing B23 ...

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... CLKOUT TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) MPC852T PowerQUICC™ Hardware Specifications, Rev B11 B12 B8 B22a B24 B25 B18 B11 B12 B22b B8 B22c B24a B25 B18 B23 B26 B19 B23 B26 B19 Freescale Semiconductor ...

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... CLKOUT B11 TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = ACS = 10, ACS = 11) MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B12 B8 B22a B27 B27a B22b B22c B18 Bus Signal Timing B23 B26 B19 27 ...

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... GPCM factors control. CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 0) MPC852T PowerQUICC™ Hardware Specifications, Rev B11 B12 B8 B22 B25 B26 B8 B30 B23 B28 B29b B29 B9 Freescale Semiconductor ...

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... CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 1) MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B11 B12 B8 B28b B28d B22 B25 B26 B28a B28c B8 Bus Signal Timing B30a B30c B23 B29c B29g B29a B29f ...

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... Bus Signal Timing CLKOUT B11 TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 1) MPC852T PowerQUICC™ Hardware Specifications, Rev B12 B8 B22 B25 B26 B8 B30b B30d B28b B28d B23 B29e B29i B29d B29h B29b B28a B28c B9 Freescale Semiconductor ...

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... UPM controls. CLKOUT A[0:31] CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 18. External Bus Timing (UPM Controlled Signals) MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B8 B31a B31d B31 B34 B34a B34b B32a B32d B32 ...

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... Figure 19. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure 20 provides the timing for the asynchronous negated UPWAIT signal that the UPM controls. CLKOUT B37 UPWAIT CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 20. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing MPC852T PowerQUICC™ Hardware Specifications, Rev B38 B38 Freescale Semiconductor ...

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... Figure 23 provides the timing for the asynchronous external master control signals negation. AS CSx, WE[0:3], OE, GPLx, BS[0:3] Figure 23. Asynchronous External Master—Control Signals Negation Timing MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B41 B42 B40 B39 B40 B43 Bus Signal Timing ...

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... CLKOUT IRQx Figure 25. Interrupt Detection Timing for External Edge Sensitive Lines MPC852T PowerQUICC™ Hardware Specifications, Rev Table 10. Interrupt Timing 1 Characteristic I39 I41 I43 All Frequencies Min Max 6.00 2.00 3.00 3.00 4 × T CLOCKOUT I40 I42 I43 Freescale Semiconductor Unit — ...

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... PCMCIA current cycle. The WAITA assertion is effective only detected 2 cycles before the PSL timer expiration. See the PCMCIA Interface section in the MPC866 PowerQUICC™ Family Reference Manual. MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 11. PCMCIA Timing 33 MHz 40 MHz Min ...

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... PCMCIA access cycle timing for the external bus read. CLKOUT TS A[0:31] REG CE1/CE2 PCOE, IORD ALE D[0:31] Figure 26. PCMCIA Access Cycles Timing External Bus Read MPC852T PowerQUICC™ Hardware Specifications, Rev P44 P46 P45 P48 P50 P52 P53 B18 P47 P49 P51 P52 B19 Freescale Semiconductor ...

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... ALE D[0:31] Figure 27. PCMCIA Access Cycles Timing External Bus Write Figure 28 provides the PCMCIA WAIT signals detection timing. CLKOUT WAITA Figure 28. PCMCIA WAIT Signals Detection Timing MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor P44 P46 P45 P48 P50 P52 P53 B8 ...

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... Figure 29. PCMCIA Output Port Timing P59 P60 Figure 30. PCMCIA Input Port Timing 50 MHz 66 MHz Max Min Max Min Max 19.00 — 19.00 — 19.00 — 18.00 — 14.40 — — 5.00 — 5.00 — — 1.00 — 1.00 — Freescale Semiconductor Unit ...

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... DSCK Figure 32 provides the timing for the debug port. DSCK DSDI DSDO MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 13. Debug Port Timing D61 D62 D61 D63 Figure 31. Debug Port Clock Input Timing D64 ...

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... Freescale Semiconductor ...

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... CLKOUT HRESET RSTCONF D[0:31] (OUT) (Weak) Figure 34. Reset Timing—Data Bus Weak Drive During Configuration MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor R71 R76 R73 R74 R75 R69 R79 ...

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... R81 Figure 36 through Figure 39. All Frequencies Min Max 100.00 — 40.00 — 0.00 10.00 5.00 — 25.00 — — 27.00 0.00 — — 20.00 100.00 — 40.00 — — 50.00 — 50.00 — 50.00 50.00 — 50.00 — Freescale Semiconductor Unit ...

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... Figure 37. JTAG Test Access Port Timing Diagram TCK TRST TCK Output Signals Output Signals Output Signals Figure 39. Boundary Scan (JTAG) Timing Diagram MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor J82 J83 J82 J84 Figure 36. JTAG Test Clock Input Timing J85 J86 J87 J88 J91 J90 Figure 38 ...

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... Port C interrupt minimum time between active edges Figure 40 shows the port C interrupt detection timing. Port C (Input) MPC852T PowerQUICC™ Hardware Specifications, Rev Table 16. Port C Interrupt Timing Characteristic 35 Figure 40. Port C Interrupt Detection Timing 33.34 MHz Unit Min Max 55 — — Freescale Semiconductor ...

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... TA assertion to rising edge of the clock setup time (applies to external TA) 1 Applies to high-to-low mode (EDM = 1). CLKO (Output) DREQ (Input) Figure 41. IDMA External Requests Timing Diagram MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Figure 41 Table 17. IDMA Controller Timing Characteristic 1 40 CPM Electrical Characteristics through Figure 44 ...

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... CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) DATA TA (Input) SDACK Figure 42. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 43. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA MPC852T PowerQUICC™ Hardware Specifications, Rev Freescale Semiconductor ...

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... Num 50 BRGO rise and fall time 51 BRGO duty cycle 52 BRGO cycle BRGOX Figure 45. Baud Rate Generator Timing Diagram MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 42 Table 18. Baud Rate Generator Timing Characteristic CPM Electrical Characteristics 45 Figure 45 ...

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... Table 19. Timer Timing Characteristic Table 20. NMSI External Clock Timing 1 Figure 46. All Frequencies Min Max 10 — 1 — 2 — 3 — All Frequencies Min Max 1/SYNCCLK — 1/SYNCCLK + 5 — — 15.00 0.00 50.00 0.00 50.00 5.00 — 5.00 — Freescale Semiconductor Unit ns clk clk clk ns Unit ...

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... CD3 setup time to RCLK3 rising edge 1 The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 3/1. 2 Also applies to CD and CTS hold time when they are used as an external sync signals. MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 2 Table 21. NMSI Internal Clock Timing Characteristic 1 2 ...

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... Figure 47. SCC NMSI Receive Timing Diagram TCLK3 102 TxD3 (Output) RTS3 (Output) CTS3 (Input) CTS3 (SYNC Input) Figure 48. SCC NMSI Transmit Timing Diagram MPC852T PowerQUICC™ Hardware Specifications, Rev 102 101 100 107 102 101 100 103 105 104 108 107 104 107 Freescale Semiconductor ...

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... TXD3 active delay (from TCLK3 rising edge) 132 TXD3 inactive delay (from TCLK3 rising edge) 133 TENA active delay (from TCLK3 rising edge) 134 TENA inactive delay (from TCLK3 rising edge) MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 102 101 100 103 104 107 105 Figure 49 ...

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... Figure 51. Ethernet Receive Timing Diagram MPC852T PowerQUICC™ Hardware Specifications, Rev Table 22. Ethernet Timing (continued) Characteristic 2 2 120 121 124 125 All Frequencies Min Max — — 20 — 20 121 123 Last Bit 126 127 Freescale Semiconductor Unit ns ns CLK ns ns ...

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... RCLK3 RxD3 0 (Input) Start Frame De- RSTRT (Output) Figure 53. CAM Interface Receive Start Timing Diagram REJECT Figure 54. CAM Interface REJECT Timing Diagram MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 128 121 132 1 1 BIT1 125 137 CPM Electrical Characteristics 129 134 ...

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... MPC852T PowerQUICC™ Hardware Specifications, Rev Figure 55 Table 23. SPI Master Timing Characteristic 167 166 160 167 162 166 Data lsb 165 164 166 Data lsb and Figure 56. All Frequencies Min Max 4 1024 2 512 15 — 0 — — — — 15 — 15 msb msb Freescale Semiconductor Unit t cyc t cyc ...

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... Slave sequential transfer delay (does not require deselect) 175 Slave data setup time (inputs) 176 Slave data hold time (inputs) 177 Slave access time MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 167 166 160 167 166 Data 165 msb ...

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... Data lsb 179 181 182 Data lsb 172 170 182 181 181 182 180 msb Data 179 176 181 182 msb Data 171 174 178 Undef msb msb 174 178 msb lsb msb lsb Freescale Semiconductor ...

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... MII_TX_ER, MII_TX_CLK) The transmitter functions correctly MII_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK frequency – 1%. MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 25. MII Receive Signal Timing FEC Electrical Characteristics ...

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... Figure 61. MII Async Inputs Timing Diagram MPC852T PowerQUICC™ Hardware Specifications, Rev Table 26. MII Transmit Signal Timing Table 27. MII Async Inputs Signal Timing M9 Min Max Unit 5 — ns — 25 — 35% 65% MII_TX_CLK period 35% 65% MII_TX_CLK period M8 Min Max Unit 1.5 — MII_TX_CLK period Freescale Semiconductor ...

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... MII_MDC pulse width low Figure 62 shows the MII serial management channel timing diagram. MII_MDC (Output) MII_MDIO (Output) MII_MDIO (Input) Figure 62. MII Serial Management Channel Timing Diagram MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Characteristic M14 M12 M13 FEC Electrical Characteristics Min Max 0 — ...

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... PBGA package. MPC852T PowerQUICC™ Hardware Specifications, Rev Temperature (Tj) Frequency (MHz) 0°C to 95° 100 –40°C to 100° 100 Order Number MPC852TVR50A MPC852TZT50A MPC852TVR66A MPC852TZT66A MPC852TVR80A MPC852TZT80A MPC852TVR100A MPC852TZT100A MPC852TCVR50A MPC852TCZT50A MPC852TCVR66A MPC852TCZT66A MPC852TCVR80A MPC852TCZT80A MPC852TCVR100A MPC852TCZT100A Freescale Semiconductor ...

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... VDDL IP_A7 IP_A2 DP3 N/C IP_A0 IP_A4 DP2 Figure 63. Pinout of PBGA Package—JEDEC Standard MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor NOTE: This is the top view of the device. BS_A0 VDDL A28 A18 A23 A19 MII_CRS BS_A3 A22 A30 A29 A27 GPL_A0 ...

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... Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Input (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional (3.3 V only) Bidirectional (3.3 V only) Bidirectional Active pull-up (3.3 V only) Freescale Semiconductor ...

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... GPL_A4 GPL_A5 E4 PORESET P1 RSTCONF K4 HRESET J4 SRESET M3 XTAL N1 MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Mechanical Data and Ordering Information Pin Number Type Bidirectional (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Output Output Output Output Output Output ...

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... Three-state (3.3 V only) Bidirectional (3.3 V only) Bidirectional (3.3 V only) Output Bidirectional (3.3 V only) Bidirectional (3.3 V only) Output Output Input (3.3 V only) Bidirectional (Optional: Open-drain) (5-V tolerant) Bidirectional (Optional: Open-drain) (5-V tolerant) Bidirectional (Optional: Open-drain) (5-V tolerant) Bidirectional (Optional: Open-drain) (5-V tolerant) Freescale Semiconductor ...

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... PC13, RTS3 E14 PC12, RTS4 E15 PC7, CTS3 J14 PC6, CD3 K15 PC5, CTS4, SDACK1 J13 MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Mechanical Data and Ordering Information Pin Number Type Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional ...

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... Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Input (5-V tolerant) Input (5-V tolerant) Input (5-V tolerant) Input (5-V tolerant) Output (5-V tolerant) Input Freescale Semiconductor ...

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... F5, F6, F7, F8, F9, F10, F11, F12, G5, G12, H5, H12, J5, J12, DDH K5, K12, L5, L6, L7, L8, L9, L10, L11, L12 N/C A1, A16, B16, C15, D14, E12, L13, M4, P15, R16, T1, T16 MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Mechanical Data and Ordering Information Pin Number Type Bidirectional (5-V tolerant) ...

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... MDIO DDL J TCK PB25 PA10 PB24 K PC5 PC7 PA8 PA9 L PD13 PA2 PC6 PA3 V DDH M N/C PC4 PA1 PB15 N PD3 PD8 PD15 V PA0 DDL P IRQ7 PD6 PD9 PD12 PD14 R D12 IRQ0 PD4 N/C PD11 T D13 D0 PD5 PD10 N MII_TXEN PD7 N Freescale Semiconductor ...

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... R5 DP1, IRQ4 R6 DP2, IRQ5 U5 DP3, IRQ6 MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 31. Pin Assignments—Non-JEDEC Pin Number Mechanical Data and Ordering Information Type Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3 ...

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... Output Output Output Output Output Output Output Output Bidirectional (3.3 V only) Output Input (3.3 V only) Input (3.3 V only) Open-drain Open-drain Analog output Analog input (3.3 V only) Output Input (3.3 V only) Output Output Output Input (3.3 V only) Input (3.3 V only) Freescale Semiconductor ...

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... PA2, CLK6, TOUT3 L15 PA1, CLK7, BRGO4, TIN4 M16 PA0, CLK8, TOUT4 N17 MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Mechanical Data and Ordering Information Pin Number Type Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3 ...

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... Bidirectional (Optional: Open-drain) (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Freescale Semiconductor ...

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... TDO, DSDO G15 MII_CRS C7 MII_MDIO H17 MII_TX_EN U15 MII_COL SSSYN MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Mechanical Data and Ordering Information Pin Number Type Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) ...

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... G6, G7, G8, G9, G10, G11, G12, G13, H6, H13, J6, J13, K6, K13, DDH L6, L13, M6, M7, M8, M9, M10, M11, M12, M13 N/C B2, B17, C17, D16, E15, F13, M14, N5, R16, T17, U2, U17 MPC852T PowerQUICC™ Hardware Specifications, Rev Pin Number Type PLL analog GND PLL analog V DD Power Power Power No connect Freescale Semiconductor ...

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... Note: Solder sphere composition is 95.5%Sn 45%Ag 0.5%Cu for MPC852TVRXXX. Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC852TZTXXX. Figure 65. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Mechanical Data and Ordering Information Figure 65 shows the mechanical ...

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... V to 50% level. 17, changed num 46 description to read, “TA assertion to rising edge ...” 42, changed TA to reflect the rising edge of the clock. Section 16.1, “Pin Assignments,” into 2 smaller sections for the JEDEC and non-JEDEC (Figure 2) and , SSSYN1 SSSYN DDSYN Freescale Semiconductor ...

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... THIS PAGE INTENTIONALLY LEFT BLANK MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Document Revision History 77 ...

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... Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC852T PowerQUICC™ Hardware Specifications, Rev Freescale Semiconductor ...

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... THIS PAGE INTENTIONALLY LEFT BLANK MPC852T PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Document Revision History 79 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...