MPC8241LZQ200D Freescale Semiconductor, MPC8241LZQ200D Datasheet - Page 21

• Manufacturer Part Number: MPC8241LZQ200D
• Description: IC MPU 32BIT 200MHZ PPC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8241LZQ200D

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 200MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: MPC82XX
• Device Core: PowerQUICC II
• Device Core Size: 32b
• Frequency (max): 200MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
Notes:
1. All PCI signals are measured from GV
2. All memory and related interface input signal specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in
3. Input timings are measured at the pin.
4. t
5. All mode select input signals specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the VM
6. The memory interface input setup and hold times are programmable to four possible combinations by programming bits 5:4
7. T
Num
10b0
10b1
10b2
10b3
11a0
11a1
11a2
11a3
question for 3.3-V PCI signaling levels. See
question to the VM = 1.4 V of the rising edge of the memory bus clock. sys_logic_clk. sys_logic_clk is the same as
PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every
rising and falling edge of PCI_SYNC_IN). See
= 1.4 V of the rising edge of the HRST_CPU/HRST_CTRL signal. See
of register offset <0x77> to select the desired input setup and hold times.
the SDRAM_SYNC_IN signal with respect to the sys_logic_clk inputs to the DLL, the resulting SDRAM clocks become offset
by the delay amount. The feedback trace length of SDRAM_SYNC_OUT to SDRAM_SYNC_IN must be shortened to
accommodate this range relative to the SDRAM clock output trace lengths to maintain phase-alignment of the memory clocks
with respect to sys_logic_clk. It is recommended that the length of SDRAM_SYNC_OUT to SDRAM_SYNC_IN be shortened
by 0.7 ns because that is the midpoint of the range of T
analyses of trace lengths and SDRAM loading must be performed to optimize timing. For details on trace measurements and
the T
10c
10d
10e
11a
11b
11c
CLK
11
os
represents a timing adjustment for SDRAM_SYNC_IN with respect to sys_logic_clk. Due to the internal delay present on
is the time of one SDRAM_SYNC_IN clock cycle.
os
problem, refer to the Freescale application note AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines.
Tap 0, register offset <0x77>, bits 5:4 = 0b00
Tap 1, register offset <0x77>, bits 5:4 = 0b01
Tap 2, register offset <0x77>, bits 5:4 = 0b10 (default)
Tap 3, register offset <0x77>, bits 5:4 = 0b11
PIC miscellaneous debug input signals valid to sys_logic_clk
(input setup)
I
Mode select inputs valid to HRST_CPU/HRST_CTRL (input setup)
T
sys_logic_clk to memory signal inputs invalid (input hold)
Tap 0, register offset <0x77>, bits 5:4 = 0b00
Tap 1, register offset <0x77>, bits 5:4 = 0b01
Tap 2, register offset <0x77>, bits 5:4 = 0b10 (default)
Tap 3, register offset <0x77>, bits 5:4 = 0b11
HRST_CPU/HRST_CTRL to mode select inputs invalid (input hold)
PCI_SYNC_IN to inputs invalid (input hold)
2
os
C input signals valid to sys_logic_clk (input setup)
—SDRAM_SYNC_IN to sys_logic_clk offset time
MPC8241 Integrated Processor Hardware Specifications, Rev. 10
Table 10. Input AC Timing Specifications (continued)
Characteristic
DD
_OV
Figure
DD
Figure
/2 of the rising edge of PCI_SYNC_IN to 0.4 × GV
12.
os
11.
and allows the impact from the range of T
Figure
13.
9 × t
Min
2.6
1.9
1.2
0.5
3.0
3.0
0.4
0.7
1.4
2.1
1.0
0
0
CLK
Electrical and Thermal Characteristics
Max
os
1.0
—
—
—
—
—
—
—
—
—
—
—
—
—
DD
to be reduced. Additional
_OV
DD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
of the signal in
Notes
2, 3–5
2, 3, 5
2, 3, 6
2, 3, 6
1, 2, 3
2, 3
2, 3
7
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