MPC8241LZQ200D Freescale Semiconductor, MPC8241LZQ200D Datasheet - Page 39

IC MPU 32BIT 200MHZ PPC 357-PBGA

MPC8241LZQ200D

Manufacturer Part Number
MPC8241LZQ200D
Description
IC MPU 32BIT 200MHZ PPC 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8241LZQ200D

Processor Type
MPC82xx PowerQUICC II 32-bit
Speed
200MHz
Voltage
1.8V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
MPC82XX
Device Core
PowerQUICC II
Device Core Size
32b
Frequency (max)
200MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.8V
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Operating Temp Range
0C to 105C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Not Compliant

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6
The PLL_CFG[0:4] are configured by the internal PLLs. For a specific PCI_SYNC_IN (PCI bus)
frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO) frequency
of operation for the PCI-to-memory frequency multiplying and the MPC603e CPU PLL (VCO) frequency
of operation for memory-to-CPU frequency multiplying. The PLL configurations are shown in
and
Freescale Semiconductor
Rev. B
Rev. D
Ref
1C
1D
1A
1B
10
12
14
16
17
19
C
B
E
0
2
3
4
6
7
7
8
9
Table
2
PLL Configuration
PLL_CFG
18.
00011
00110
00111
[0:4]
00000
00010
00100
00111
01000
01001
01011
01100
01110
10000
10010
10100
10110
10111
11001
11010
11011
11100
11101
1
6
9
6
38
50
PCI Clock
SYNC_IN)
25–27
50
Range
34
50
50
30
37
25–41
25–27
(MHz)
33
44
Input
(PCI_
4
4
4
–41
–55
4
7
4
4
4
MPC8241 Integrated Processor Hardware Specifications, Rev. 10
–55
–37
–66
–55
–33
–41
5,13
5,13
5,11
5,11
5,11
5
5
5
3
5
5
5
3
5
166 MHz-Part
Table 17. PLL Configurations (166- and 200-MHz)
Not available
Not available
Not available
Not available
Peripheral
Bus Clock
Bypass
Range
Logic/
(MHz)
34–37
50–66
50–82
50–55
50–55
76–82
60–66
50–54
75–83
75–83
37–41
Mem
66
66
2
153–166
100–132
100–164
150–166
150–166
152–164
150–165
150–162
150–166
150–166
150–166
Range
Clock
(MHz)
CPU
165
166
38
PCI Clock
SYNC_IN)
25–44
25–33
33
44
Range
34
50
50
50
30
50
37
25–33
25–28
25-26
(MHz)
33
44
Input
(PCI_
4
13
13
–50
44
25
25
4
7
4
4
4
4
4
–44
–66
–66
–66
–40
–66
–50
5,13
5,13
–40
–53
5
5
5
8,10
5,12
Not available
5,12
5
5
5
5
3
3
3
5
3
5
3
5
5
200-MHz Part
Peripheral
Mem Bus
Bypass
76–100
75–100
Range
Logic/
Clock
(MHz)
34–44
50–66
50–88
50–66
50–66
60–80
60–66
75–99
50–56
66–80
37–50
66–80
75-78
100
66
50
66
66
2
153–200
100–132
100–176
150–198
150–198
152–200
150–200
150–198
150–200
150–198
175–196
165–200
150–200
165–200
188-195
Range
Clock
(MHz)
CPU
198
200
200
198
198
(Mem VCO)
1 (Bypass)
1 (Bypass)
PCI-to-
Bypass
1.5 (2)
1.5 (2)
1.5(2)
Mem
3 (2)
1 (4)
2 (4)
1 (4)
2 (2)
2 (4)
2 (4)
3 (2)
2 (4)
1 (4)
2(2)
2(4)
4(2)
2(2)
2(2)
Multipliers
PLL Configuration
(CPU VCO)
Table 17
Mem-to-
Bypass
2.5 (2)
4.5 (2)
2.5 (2)
3.5 (2)
2.5 (2)
2.5(2)
2.5(2)
CPU
2 (4)
2 (4)
3 (2)
3 (2)
2 (2)
3 (2)
2 (2)
2 (2)
4 (2)
4(2)
2(2)
3(2)
3(2)
39

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