MPC8241LZQ200D Freescale Semiconductor, MPC8241LZQ200D Datasheet - Page 42

• Manufacturer Part Number: MPC8241LZQ200D
• Description: IC MPU 32BIT 200MHZ PPC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8241LZQ200D

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 200MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: MPC82XX
• Device Core: PowerQUICC II
• Device Core Size: 32b
• Frequency (max): 200MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

System Design Information
7
This section provides electrical and thermal design recommendations for successful application of the
MPC8241.
7.1
The AV
PLL and the MPC603e processor PLL. To ensure stability of the internal clocks, the power supplied to the
AV
frequency range of the PLLs. Two separate circuits similar to the one shown in
mount capacitors with minimum effective series inductance (ESL) is recommended for AV
power signal pins. In High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), Dr.
Howard Johnson recommends using multiple small capacitors of equal value instead of multiple values.
42
Notes:
1. Limited by maximum PCI input frequency (66 MHz).
2. Note the impact of the relevant revisions for modes 7 and 1E.
3. Limited by minimum memory VCO frequency (132 MHz).
4. Limited due to maximum memory VCO frequency (352 MHz).
5. Limited by maximum CPU operating frequency.
6. Limited by minimum CPU VCO frequency (300 MHz).
7. Limited by maximum CPU VCO frequency (704 MHz).
8. In clock off mode, no clocking occurs inside the MPC8241, regardless of the PCI_SYNC_IN input.
9. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity.
10.PLL_CFG[0:4] settings that are not listed are reserved.
11.Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.
12.In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is
13.In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral logic
14.Limited by minimum CPU operating frequency (100 MHz).
15.Limited by minimum memory bus frequency (50 MHz).
DD
disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware modeling. The
AC timing specifications in this document do not apply in PLL bypass mode.
PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this mode, the OSC_IN input
signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation and the processor PLL is disabled. The
PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This mode is intended for hardware modeling.
The AC timing specifications in this document do not apply in dual PLL bypass mode.
Ref
1F
and AV
2
System Design Information
DD
PLL Power Supply Filtering
and AV
CFG[0:4]
DD
11111
PLL_
2 input signals should be filtered of any noise in the 500 kHz to 10 MHz resonant
DD
2 power signals on the MPC8241 provide power to the peripheral logic/memory bus
8
10,11
MPC8241 Integrated Processor Hardware Specifications, Rev. 10
Table 18. PLL Configurations (266-MHz Parts) (continued)
PCI Clock Input
(PCI_SYNC_IN)
Range
(MHz)
1
266-MHz Part
Not usable
Periph Logic/
Clock Range
Mem Bus
(MHz)
9
CPU Clock
Range
(MHz)
PCI-to-Mem
(Mem VCO)
Figure 26
Off
Freescale Semiconductor
Multipliers
DD
using surface
Mem-to-CPU
(CPU VCO)
and AV
Off
DD
2