MPC5200CVR400B Freescale Semiconductor, MPC5200CVR400B Datasheet - Page 28

• Manufacturer Part Number: MPC5200CVR400B
• Description: IC MPU 32BIT 400MHZ 272-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC5200CVR400B

• Processor Type: MPC52xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 272-PBGA
• Processor Series: MPC52xx
• Core: e300
• Development Tools By Supplier: MEDIA5200KIT1E
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 2.5 V, 3.3 V
• Minimum Operating Temperature: - 40 C
• Core Size: 32 Bit
• No. Of I/o's: 56
• Ram Memory Size: 16KB
• Cpu Speed: 400MHz
• No. Of Timers: 8
• Embedded Interface Type: CAN, I2C, SCI, SPI
• No. Of Pwm Channels: 8
• Digital Ic Case Style: TEPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Electrical and Thermal Characteristics
3.3.7
The Local Plus Bus is the external bus interface of the MPC5200. Maximum eight configurable
Chip-selects are provided. There are two main modes of operation: non-MUXed (Legacy and Burst) and
MUXED. The reference clock is the PCI CLK. The maximum bus frequency is 66 MHz.
Definition of Acronyms and Terms:
WS = Wait State
DC = Dead Cycle
LB = Long Burst
DS = Data size in Byte
tPCIck = PCI clock period
tIPBIck = IPBI clock period
3.3.7.1
28
Sym
t
t
CSN
CSA
t
t
t
t
t
t
t
t
t
t
t
t
t
10
11
12
13
3
4
5
6
7
8
9
1
2
PCI CLK to CS assertion
PCI CLK to CS negation
CS pulse width
ADDR valid before CS assertion
ADDR hold after CS negation
OE assertion before CS assertion
OE negation before CS negation
RW valid before CS assertion
RW hold after CS negation
DATA output valid before CS assertion
DATA output hold after CS negation
DATA input setup before CS negation
DATA input hold after CS negation
ACK assertion after CS assertion
ACK negation after CS negation
Local Plus Bus
Non-MUXed Mode
Figure 11. Timing Diagram—IPBI and PCI clock (example ratio: 4:1)
PCI CLK
IPBI CLK
Description
Table 24. Non-MUXed Mode Timing
MPC5200 Data Sheet, Rev. 4
tPCIck
tIPBIck
(2+WS)*t
t
t
t
t
t
t
t
IPBIck
IPBIck
IPBIck
IPBIck
IPBIck
PCIck
PCIck
Min
2.8
0
-
-
-
-
-
PCIck
(2+WS)*t
(DC+1)*t
t
t
Max
PCIck
PCIck
0.4
0.4
1.8
1.8
-
-
-
-
-
-
-
PCIck
PCIck
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Freescale Semiconductor
Notes SpecID
1
2
3
3
A7.12
A7.10
A7.11
A7.13
A7.14
A7.15
A7.1
A7.2
A7.3
A7.4
A7.5
A7.6
A7.7
A7.8
A7.9