MPC8314ECVRAFDA Freescale Semiconductor, MPC8314ECVRAFDA Datasheet

Page 1

... The MPC8314E incorporates the e300c3 (MPC603e-based) core, which includes 16 Kbytes of L1 instruction and data caches, on-chip memory management units (MMUs), and floating-point support. In addition to the e300 core, the SoC © Freescale Semiconductor, Inc., 2009. All rights reserved. Document Number: MPC8314EEC ™ II Pro Processor 1 ...

Page 2

... Express On-Chip x1 ULPI HS PHY Note: The MPC8314 do not include a security engine. Figure 1. MPC8314E Block Diagram ™ II Pro Processor Hardware Specifications, Rev. 0 Figure 1. Enhanced DDR1/DDR2 Local Bus, TDM Controller SPI eTSEC eTSEC RGMII, (R)MII RGMII, (R)MII RTBI, SGMII RTBI, SGMII Freescale Semiconductor ...

Page 3

... Random number generator (RNG) — Combines a True Random Number Generator (TRNG) and a NIST-approved Pseudo-Random Number Generator (PRNG) (as described in Annex C of FIPS140-2 and ANSI X9.62). • Cyclical Redundancy Check Hardware Accelerator (CRCA) MPC8314E PowerQUICC Freescale Semiconductor ™ II Pro Processor Hardware Specifications, Rev. 0 MPC8314E Features 3 ...

Page 4

... The TDM Transmitter Sync Signal (TFS), Transmitter Clock Signal (TCK) and Receiver Clock • Signal (RCK) can be configured as either input or output • Frame sync and data signals can be programmed to be sampled either on the rising edge or on the falling edge of the clock MPC8314E PowerQUICC 4 ™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor ...

Page 5

... Two controllers designed to comply with IEEE Std 802.3™, IEEE 802.3u™, IEEE 802.3x™, IEEE 802.3z™, IEEE 802.3au™, IEEE 802.3ab™, and IEEE Std 1588™ MPC8314E PowerQUICC Freescale Semiconductor ™ II Pro Processor Hardware Specifications, Rev. 0 MPC8314E Features ...

Page 6

... Timers The integrated four-channel DMA controller includes the following features: • Allows chaining (both extended and direct) through local memory-mapped chain descriptors (accessible by local masters) MPC8314E PowerQUICC DUART, Enhanced Local Bus Controller ™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor ...

Page 7

... DDR2 DRAM I/O supply voltage PCI, local bus, DUART, system control and power 2 management Ethernet management, 1588 timer and JTAG I/O voltage USB, and eTSEC I/O voltage MPC8314E PowerQUICC Freescale Semiconductor Table 1. Absolute Maximum Ratings Symbol VDD AVDD GVDD GVDD NVDD LVDD ™ ...

Page 8

... II Pro Processor Hardware Specifications, Rev. 0 Max Value Unit Notes –0.3 to 1.26 V — –0.3 to 3.6 V — –0.3 to 1.26 V — °C –55 to150 — Figure 2. Table 2 Status in D3 Unit Notes Warm mode V Switched Off — V — — V Switched Off — Freescale Semiconductor ...

Page 9

... Analog and digital ground Junction temperature range Note: 1. The NVDDx_ON are static power supplies and can be connected together. 2. The NVDDx_OFF are switchable power supplies and can be connected together. 3. Minimum Temperature is specified with T MPC8314E PowerQUICC Freescale Semiconductor Recommended Symbol 1 Value XPADVSS 0.0 SDAVDD 1.0 ± ...

Page 10

... During the power ramp up, before the power supplies are stable, if the I/O voltages are supplied MPC8314E PowerQUICC 10 GND Not to Exceed 10 interface Table 3. Output Drive Capability Output Impedance (Ω ™ II Pro Processor Hardware Specifications, Rev Supply Voltage NVDD = 3.3 V GVDD = 2.5 V GVDD = 1.8 V NVDD = 3.3 V NVDD = 3.3 V LVDD = 3 2.5 V Freescale Semiconductor ...

Page 11

... I/O pins, with the exception of wake-up pins, must be turned off. Applying supplied external voltage to any I/O pins, except the wake up pins, while the device warm standby mode may cause permanent damage to the device. MPC8314E PowerQUICC Freescale Semiconductor V 0.7 V 90% t Power sequence for switchable power supplies Figure 3 ...

Page 12

... II Pro Processor Hardware Specifications, Rev. 0 Switchable I/O Voltage (GVDD, LVDDx_OFF, NVDDx_OFF) Switchable Core Voltage (VDD >= 32 clock PCI_SYNC_IN Table . 4 1,3 1,2 Maximum Unit 1.646 W 1.665 W 1.690 W = 105•C, and an artificial smoker C, and an artificial smoker j Freescale Semiconductor ...

Page 13

... PCIe two 2.5 GHz — x1lane Other I/O — — 5 Clock Input Timing This section provides the clock input DC and AC electrical characteristics for the MPC8314E. MPC8314E PowerQUICC Freescale Semiconductor Table 5. MPC8314E Power Dissipation LVDD1_OFF/ LVDD2 LVDD2_ON _ON (3.3 V) (3.3V) (3 ...

Page 14

... II Pro Processor Hardware Specifications, Rev. 0 Min Max Unit 2.4 NVDD + 0.3 V -0.3 0.4 V μA — ±10 μA — ±40 μA — ±10 μA — ±10 μA — ±10 μA — ±40 Table 7 provides the clock Max Unit Notes 66 MHz 41 1 ±150 Freescale Semiconductor ...

Page 15

... CFG_SYS_CLKIN_DIV) with respect to negation of PORESET when the device is in PCI agent mode Input hold time for POR configuration signals with respect to negation of HRESET Time for the device to turn off POR configuration signals with respect to the assertion of HRESET MPC8314E PowerQUICC Freescale Semiconductor Symbol Condition V — — ...

Page 16

... II Pro Processor Hardware Specifications, Rev — t PCI_SYNC_IN Max Unit Notes μs 100 — μs 100 — μs 100 — μs 100 — Max Unit Notes 1.9 V 0.51 × GVDD V MVREF + 0.04 V GVDD + 0.3 V — MVREF – 0.125 V — μA 9.9 4 — mA — Freescale Semiconductor ...

Page 17

... Peak-to-peak noise on MVREF may not exceed ±2% of the DC value not applied directly to the device the supply to which far end signal termination is made and is expected equal to MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled MPC8314E PowerQUICC Freescale Semiconductor Symbol Min I 13.4 OL ≤ ...

Page 18

... II Pro Processor Hardware Specifications, Rev. 0 Min Max Unit Notes — 0 GVDD/2, V (peak-to-peak) = 0.2 V. OUT OUT REF Max Unit Note μA 500 1 Max Unit Notes MVREF – 0.45 V — V Max Unit MVREF – 0.51 V — V Freescale Semiconductor 1 1 — — Notes ...

Page 19

... CISKEW Figure 5 shows the DDR SDRAM input AC timing for the tolerated MDQS to MDQ skew (t MCK[n] MCK[n] MDQS[n] MDQ[x] MPC8314E PowerQUICC Freescale Semiconductor Symbol Min t CISKEW 266 MHz –875 200 MHz –1250 )) where T is the clock period and abs(t CISKEW ...

Page 20

... II Pro Processor Hardware Specifications, Rev. 0 Max Unit Notes — — ns — — ns — — ns — — 0 — — ps — — –0.5 × t – 0.6 + 0.6 ns MCK 0.6 ns memory clock MCK describes the DDR timing DDKHMH can be modified through DDKHMH follows the DDKHMP Freescale Semiconductor for ...

Page 21

... MDQS MDQS Figure 7 shows the DDR and DDR2 SDRAM output timing diagram. MCK MCK ADDR/CMD Write A0 MDQS[n] MDQ[x] Figure 7. DDR and DDR2 SDRAM Output Timing Diagram MPC8314E PowerQUICC Freescale Semiconductor t MCK t = 0.6 ns DDKHMH(max –0.6 ns DDKHMH(min) Figure 6. Timing Diagram for t DDKHMH t MCK ...

Page 22

... Figure 8. DDR AC Test Load Table 22. DUART AC Timing Specifications Parameter > 1,000,000 ™ II Pro Processor Hardware Specifications, Rev. 0 GVDD Ω Symbol Min Max V 2.1 NVDD + 0 –0.3 0 NVDD – 0.2 — — 0 — ± Value Unit Notes 256 baud — baud 1 16 — 2 Freescale Semiconductor Unit μA ...

Page 23

... Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Note: 1. The symbol this case, represents the LV IN MPC8314E PowerQUICC Freescale Semiconductor Section 9.3, “Ethernet Management Symbol Conditions LVDD — — –4.0 mA LVDD = Min ...

Page 24

... LVDD + 0.3 V – 0.3 0.40 SS 1.7 LVDD + 0.3 –0.3 0.70 — 15 –15 — Table 1 and Table 2. Min Typ Max — 400 — — 40 — 35 — 1.0 — 4.0 1.0 — 4.0 symbolizes MII transmit MTKHDX Freescale Semiconductor Unit μA μA Unit for ...

Page 25

... For example, the subscript of t MRX used with the appropriate letter: R (rise (fall). Figure 10 provides the AC test load for eTSEC. Output MPC8314E PowerQUICC Freescale Semiconductor t MTX t t MTXH MTXF t MTKHDX Figure 9 ...

Page 26

... RMII(RM) reference (X) clock. For rise and fall RMX ™ II Pro Processor Hardware Specifications, Rev MRXR t MRDXKH Table 27 provides the Min Typ Max — 20 — 35 — — 10 1.0 — 4.0 1.0 — 4.0 for outputs. For example, t RMTKHDX Freescale Semiconductor Unit ...

Page 27

... Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of t times, the latter convention is used with the appropriate letter: R (rise (fall). Figure 13 provides the AC test load. Output MPC8314E PowerQUICC Freescale Semiconductor t RMX t t RMXH RMXF ...

Page 28

... RTBI (T) receive (RX) clock. Note also that the RGT ™ II Pro Processor Hardware Specifications, Rev RMXR t RMRDXKH Min Typ Max –0.6 — 0.6 1.0 — 2.6 7.2 8.0 8 — — 0.75 — — 0.75 — 8.0 — 47 — the lowest speed transitioned RGT Freescale Semiconductor Unit ...

Page 29

... The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 30. MII Management DC Electrical Characteristics Powered at 3.3 V Parameter Supply voltage (3.3 V) Output high voltage Output low voltage Input high voltage Input low voltage MPC8314E PowerQUICC Freescale Semiconductor t RGTH t SKRGT TXD[8:5] TXD[3:0] TXD[7:4] TXD[9] TXD[4] ...

Page 30

... Min Max Unit μA — 40 μA –600 — Table 1 and Table 2. Typ Max Unit Notes 2.5 — MHz 2 400 — ns — — — ns — — 170 ns 3 — — ns — — — ns — — — — — symbolizes MDKHDX Freescale Semiconductor ...

Page 31

... Input high voltage Input low voltage Input current 9.4.2 1588 Timer AC Specifications Table 33 provides the 1588 timer AC specifications. Parameter Timer clock cycle time Input setup to timer clock Input hold from timer clock MPC8314E PowerQUICC Freescale Semiconductor t MDC t t MDCF MDCH t MDDVKH t MDDXKH t ...

Page 32

... AC-Coupled capacitor. Each TX Figure 48. as long as such termination does not violate SD_REF_CLK and SD_REF_CLK ™ II Pro Processor Hardware Specifications, Rev. 0 Min Max Unit — — — Min Typical Max Units Notes - — — 100 ps –50 — Freescale Semiconductor Notes 2 — — — ...

Page 33

... OS 5. The |V | value shown in the Typ column is based on the condition of XCOREVDD 500 mV), SerDes transmitter is terminated with 100-Ω differential load between TX[n] and TX[n]. OS MPC8314E PowerQUICC Freescale Semiconductor . Symbol Min Typ 0.95 VOH — VOL ...

Page 34

... TXm TXn 50 Ω 50 Ω 50 Ω 50 Ω TXn Symbol Min Typ XCOREVDD 0.95 1.0 — N/A V 100 — RX_DIFFp-p 175 — ™ II Pro Processor Hardware Specifications, Rev Ω Receiver 50 Ω 50 Ω Transmitter 50 Ω Max Unit Notes 1.05 V — — 1 1200 Freescale Semiconductor ...

Page 35

... At recommended operating conditions with XCOREVDD = 1.0V ± 5%. Parameter Deterministic Jitter Total Jitter Unit Interval V fall time (80%-20 rise time (20%-80%) OD Notes: 1. Each UI is 800 ps ± 100 ppm. MPC8314E PowerQUICC Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management Symbol Min Typ VLOS 30 — 65 — V — — CM_ACp-p ...

Page 36

... JDR 0.55 — JSIN 0.1 — JT 0.65 — BER — — UI 799.92 800 C 5 — TX ™ II Pro Processor Hardware Specifications, Rev. 0 Max Unit Notes — UI p-p 1 — UI p-p 1 — UI p-p 1 — UI p-p 1 -12 10 — 800. 200 nF 3 Freescale Semiconductor ...

Page 37

... Figure 19. SGMII Receiver Input Compliance Mask Figure 20. SGMII AC Test/Measurement Load 10 USB 10.1 USB Dual-Role Controllers This section provides the AC and DC electrical specifications for the USB-ULPI interface. MPC8314E PowerQUICC Freescale Semiconductor 0.275 0.4 0.6 Time (UI) ™ II Pro Processor Hardware Specifications, Rev. 0 USB 1 0 ...

Page 38

... II Pro Processor Hardware Specifications, Rev. 0 Min Max 2 LVDD + 0.3 IH –0.3 0 — ±5 IN LVDD – 0.2 — OH — 0.2 OL Table 1 and Table 2. Min Max Unit 15 — — — ns — — ns symbolizes USB timing USIXKH NVDD Ω Freescale Semiconductor Unit V V μ Notes for USKHOX ...

Page 39

... Table 42 provides the USB clock input (USB_CLK_IN) AC timing specifications. Table 42. USB_CLK_IN AC Timing Specifications Parameter/Condition Frequency range Clock frequency tolerance Reference clock duty cycle Total input jitter/Time interval error MPC8314E PowerQUICC Freescale Semiconductor t USIVKH t t USKHOX USKHOV Figure 22. USB Signals Symbol Min V 2 ...

Page 40

... LBIVKH t LBIXKH t LBOTOT1 t LBOTOT2 t LBOTOT3 ™ II Pro Processor Hardware Specifications, Rev. 0 Min Max NVDD – 0.2 — OH — 0 NVDD + 0.3 IH –0.3 0.8 IL — ±5 IN Min Max Unit 15 — — ns 1.0 — ns 1.5 — — ns 2.5 — ns Freescale Semiconductor Unit μA Notes ...

Page 41

... For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Figure 23 provides the AC test load for the local bus. Output MPC8314E PowerQUICC Freescale Semiconductor 1 Symbol t LBKHOV t ...

Page 42

... UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV MPC8314E PowerQUICC 42 t LBIVKH t LBKHOV t LBKHOZ t LBKHOV t LBOTOT t LBKHOZ t LBKHOV t LBIVKH t LBKHOZ t LBKHOV ™ II Pro Processor Hardware Specifications, Rev LBIXKH t LBIVKH t LBIXKH t LBIXKH t LBIXKH t LBIXKH t LBIVKH Freescale Semiconductor ...

Page 43

... DC electrical characteristics for the IEEE 1149.1 (JTAG) interface. Table 45. JTAG Interface DC Electrical Characteristics Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage MPC8314E PowerQUICC Freescale Semiconductor t LBKHOZ t LBKHOV t LBIVKH t t LBKHOZ ...

Page 44

... II Pro Processor Hardware Specifications, Rev. 0 Table 46 through Figure 31. 1 Min Max Unit Notes 0 33.3 MHz 30 — — — — 4 — — 10 — — 2 — the midpoint of the signal in question. TCLK Table 27). symbolizes JTAG JTDVKH clock JTG Freescale Semiconductor — — — — ...

Page 45

... TRST timing diagram. TRST Figure 30 provides the boundary-scan timing diagram. JTAG External Clock Boundary Data Inputs t JTKLDX Boundary Data Outputs Boundary Output Data Valid Data Outputs MPC8314E PowerQUICC Freescale Semiconductor = 50 Ω JTKHKL t JTG VM = Midpoint Voltage (NVDD/ TRST VM = Midpoint Voltage (NVDD/2) Figure 29 ...

Page 46

... Input Data Valid Output Data Valid 2 C interface of the MPC8314E. Min Max Unit 0.7 × NVDD NVDD + 0.3 V 0.3 × NVDD –0.3 V 0.2 × NVDD 0 V 0.8 × NVDD NVDD + 0 0.1 × C 250 — Freescale Semiconductor Notes — — 1 — — ...

Page 47

... Data hold time: Fall time of both SDA and SCL signals Setup time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) MPC8314E PowerQUICC Freescale Semiconductor Electrical Characteristics (continued) Symbol interface ...

Page 48

... II Pro Processor Hardware Specifications, Rev Symbol Min Max 0.2 × NVDD V — symbolizes I I2DVKH clock reference (K) going to I2C of the SCL signal) to bridge the IHmin ) of the SCL signal. I2CL NVDD Ω I2CF t I2CR t I2PVKH P S Freescale Semiconductor Unit V for C timing I2PVKH ...

Page 49

... For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. MPC8314E PowerQUICC Freescale Semiconductor Symbol Test Condition ≥ V ...

Page 50

... PCI timing (PC) with respect to PCRHFV = 50 Ω Ω Figure 34. PCI AC Test Load t PCIVKH t PCIXKH ™ II Pro Processor Hardware Specifications, Rev. 0 Max Unit Notes — — — for outputs. For example, t PCIVKH NVDD/2 Freescale Semiconductor ...

Page 51

... The Differential Output Voltage (or Swing) of the transmitter, V the two complimentary output voltages: V negative. 3. Differential Input Voltage, V The Differential Input Voltage (or Swing) of the receiver, V two complimentary input voltages Differential Peak Voltage, V MPC8314E PowerQUICC Freescale Semiconductor t PCKHOV (or Differential Output Swing): OD – V The V TXn TXn ...

Page 52

... B| Volts. DIFFp DIFFp |(A - B)| Volts, which is twice of differential DIFFp-p DIFFp = 2*|V TX-DIFFp-p OD Figure example for differential waveform. cm Differential Swing Differential Peak Voltage, V Differential Peak-Peak Voltage, V DIFFpp ™ II Pro Processor Hardware Specifications, Rev cm_out DIFFp = 2*V (not shown) DIFFp Freescale Semiconductor = (V TXn ...

Page 53

... XCOREVSS DC exceeds the maximum input current limitations, then it must be AC-coupled off-chip. • The input amplitude requirement — This requirement is described in detail in the following sections. MPC8314E PowerQUICC Freescale Semiconductor is 500 mV in one phase and –500 mV in the other 500 mV. The peak-to-peak differential voltage (V DIFFp ™ ...

Page 54

... AC-coupled externally. For the best noise performance, the reference of the clock could be DC MPC8314E PowerQUICC 54 50 Ω Input Amp 50 Ω Figure 39 shows the SerDes reference clock input requirement Figure 40 shows the SerDes reference clock input ™ II Pro Processor Hardware Specifications, Rev. 0 Figure 41 shows Freescale Semiconductor ...

Page 55

... Interfacing With Other Differential Signaling Levels With on-chip termination to XCOREVSS, the differential reference clocks inputs are HCSL (High-Speed Current Steering Logic) compatible DC-coupled. MPC8314E PowerQUICC Freescale Semiconductor ™ II Pro Processor Hardware Specifications, Rev. 0 High-Speed Serial Interfaces (HSSI) Vmax < 800 mV 100 mV < Vcm < 400 mV Vmin > ...

Page 56

... They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended ...

Page 57

... R2 = 25Ω. Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular clock driver chip. MPC8314E PowerQUICC Freescale Semiconductor SD_REF_CLK 100 Ω differential PWB trace SD_REF_CLK ™ ...

Page 58

... SD_REF_CLK Total 50 Ω. Assume clock driver’s output impedance is about 16 Ω. SD_REF_CLK 100 Ω differential PWB trace SD_REF_CLK Ω 50 ™ II Pro Processor Hardware Specifications, Rev. 0 MPC8315E 50 Ω SerDes Refer. CLK Receiver 50 Ω MPC8315E 50 Ω SerDes Refer. CLK Receiver 50 Ω Freescale Semiconductor ...

Page 59

... IH 0 –200 IL SDn_REF_CL K minus Figure 46. Differential Measurement Points for Rise and Fall Time SDn_REF_CLK SDn_REF_CLK Figure 47. Single-Ended Measurement Points for Rise and Fall Time Matching MPC8314E PowerQUICC Freescale Semiconductor Symbol Rise Edge Rate Fall Edge Rate V +200 Rise-Fall Matching Figure 46. ...

Page 60

... DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK For more information, see Section 15.2, “SerDes Reference MPC8314E PowerQUICC 60 RXn TXn 50 Ω 50 Ω TXn RXn Characteristics” Clocks.” ™ II Pro Processor Hardware Specifications, Rev. 0 SD_REF_CLK” Clocks” 50 Ω Receiver 50 Ω Freescale Semiconductor ...

Page 61

... Unit interval Differential peak-to-peak V TX-DIFFp-p output voltage De-Emphasized V TX-DE-RATIO differential output voltage (ratio) Minimum TX eye width T TX-EYE MPC8314E PowerQUICC Freescale Semiconductor Comments UI Each UI is 400 ps ± 300 ppm. UI does not account for Spread Spectrum Clock dictated variations 2*|V TX-DIFFp-p TX- TX-D- Ratio of the V ...

Page 62

... The total current the Transmitter can provide when shorted to its ground ™ II Pro Processor Hardware Specifications, Rev. 0 Min Typical Max Units — — 0. 0.125 — — — — — 100 — — — — 600 mV — — 3.6 V — — Freescale Semiconductor Notes — ...

Page 63

... Transmitter DC Z TX-DC impedance Lane-to-Lane output skew L TX-SKEW AC coupling capacitor C MPC8314E PowerQUICC Freescale Semiconductor Comments Minimum time a Transmitter must be in Electrical Idle Utilized by the Receiver to start looking for an Electrical Idle Exit after successfully receiving an Electrical Idle ordered set After sending an Electrical ...

Page 64

... II Pro Processor Hardware Specifications, Rev. 0 Min Typical Max Units Notes 0 — Figure 51 and measured over Figure 49.) = 0.30 UI for the TX-JITTER-MAX median is less than half of the total Figure 51). Note that the series capacitors, Figure 51 for both V and V TX-D+ TX-D- Freescale Semiconductor 7 . ...

Page 65

... Table 55. Differential Receiver (RX) Input Specifications Parameter Symbol Unit interval Differential peak-to-peak V RX-DIFFp-p output voltage Minimum receiver eye T RX-EYE width MPC8314E PowerQUICC Freescale Semiconductor = 0 mV TX-DIFF [Transition Bit 800 mV TX-DIFFp-p-MIN [De-emphasized Bit] 566 mV (3 dB) >= V >= 505 mV (4 dB) TX-DIFFp-p-MIN 0 – 0.3 UI(J TX-TOTAL-MAX ...

Page 66

... II Pro Processor Hardware Specifications, Rev. 0 Min Typical Max Units — — 0 — — 150 mV 15 — — — — dB Ω 80 100 120 Ω Ω 200 k — — — 175 mV — — Freescale Semiconductor Notes — — ...

Page 67

... RX component designer should provide additional margin to adequately compensate for the degraded minimum Receiver eye diagram (shown in adequate combination of system simulations and the return loss measured looking into the RX package MPC8314E PowerQUICC Freescale Semiconductor Comments Skew across all lanes on a Link. This includes variation in the length of SKP ordered set (e ...

Page 68

... D+ and D– not being exactly matched in length at the package pin boundary. MPC8314E PowerQUICC 68 NOTE Figure 51). Note that the series capacitors > 175 mV RX-DIFFp-p-MIN 0 RX-EYE-MIN NOTE ™ II Pro Processor Hardware Specifications, Rev PEACCTX RX-DIFF (D+ D– Crossing Point) Figure 51. Freescale Semiconductor ...

Page 69

... Characteristic Timers inputs—minimum pulse width Notes: 1. Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any external synchronous logic. Timers input are required to be valid for at least t MPC8314E PowerQUICC Freescale Semiconductor Symbol Condition –8.0 mA ...

Page 70

... R L Figure 53. GPIO AC Test Load ™ II Pro Processor Hardware Specifications, Rev. 0 NVDD/2 Min Max Unit 2.4 — V — 0.5 V — 0.4 V 2.1 NVDD + 0.3 V –0.3 0.8 V μA — ± Symbol Min Unit PIWID ns to ensure proper operation. NVDD/2 Freescale Semiconductor ...

Page 71

... This section describes the DC and AC electrical specifications for the SPI of the MPC8314E. 20.1 SPI DC Electrical Characteristics Table 62 provides the DC electrical characteristics for the SPI. Characteristic Input high voltage Input low voltage MPC8314E PowerQUICC Freescale Semiconductor Table 60. IPIC DC Electrical Characteristics Symbol Condition V — — ...

Page 72

... Symbol Min Max t — 6 NIKHOV t 0.5 NIKHOX t — 8.5 NEKHOV t 2 — NEKHOX t 6 — NIIVKH t 0 — NIIXKH t 4 — NEIVKH t 2 — NEIXKH symbolizes the internal NIKHOX NVDD Ω Freescale Semiconductor Unit μ Unit for ...

Page 73

... TDM DC Electrical Characteristics Table 64 provides the DC electrical characteristics TDM. Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current MPC8314E PowerQUICC Freescale Semiconductor t NEIXKH t NEKHOV t NIIXKH t NIIVKH t NIKHOV Table 64. TDM DC Electrical Characteristics ...

Page 74

... Figure 57. TDM Receive Signals ™ II Pro Processor Hardware Specifications, Rev. 0 Min Max Units 20.0 — ns 8.0 — ns 8.0 — ns 3.0 — ns 3.5 — ns 2.0 — ns 4.0 — ns — 14.0 ns 2.0 — ns — 10.0 ns — 13.5 ns 2.5 — ns symbolizes TDM TDMIVKH , reference ( DMFSKHOX Freescale Semiconductor ...

Page 75

... Package Parameters for the MPC8314E TEPBGA II The package parameters are as provided in the following list. The package type × 29 mm, TEPBGA II. Package outline Interconnects Pitch Module height (typical) Solder balls Ball diameter (typical) MPC8314E PowerQUICC Freescale Semiconductor DM_HIGH DM_LOW t DMTKHOV t DM_OUTAC ...

Page 76

... Datum A, the seating plane, is determined by the spherical crowns of the solder balls. Figure 59. Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II 22.3 Pinout Listings Table 66 provides the pin-out listing for the TEPBGA II package. MPC8314E PowerQUICC 76 ™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor ...

Page 77

... MEMC_MDQ[15] MEMC_MDQ[16] MEMC_MDQ[17] MEMC_MDQ[18] MEMC_MDQ[19] MEMC_MDQ[20] MEMC_MDQ[21] MEMC_MDQ[22] MEMC_MDQ[23] MEMC_MDQ[24] MEMC_MDQ[25] MEMC_MDQ[26] MEMC_MDQ[27] MEMC_MDQ[28] MEMC_MDQ[29] MEMC_MDQ[30] MPC8314E PowerQUICC Freescale Semiconductor Package Pin Number DDR Memory Controller Interface AF16 AE17 AH17 AG17 AG18 AH18 AD18 AF19 AH19 AD19 AG20 AH20 AH21 AE21 ...

Page 78

... O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — Freescale Semiconductor ...

Page 79

... LAD8 LAD9 LAD10 LAD11 LAD12 LAD13 LAD14 LAD15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 MPC8314E PowerQUICC Freescale Semiconductor Package Pin Number Pin Type AE4 AF4 AF3 AF1 AE1 AE3 AD4 AD12 Local Bus Controller Interface AB28 AB27 AC28 AA24 AC27 ...

Page 80

... NVDD3 — _OFF O NVDD3 — _OFF O NVDD2 — _OFF I/O NVDD2 — _OFF I/O NVDD2 — _OFF O NVDD2 — _OFF O NVDD2 — _OFF I/O NVDD2 — _OFF I NVDD2 — _OFF O NVDD2 — _OFF I/O NVDD4 2 _OFF I/O NVDD4 2 _OFF Freescale Semiconductor ...

Page 81

... IRQ[2] IRQ[3] IRQ[4] IRQ[5]/CORE_SRESET_IN IRQ[6] /CKSTOP_OUT IRQ[7]/CKSTOP_IN CFG_CLKIN_DIV EXT_PWR_CTRL PMC_PWR_OK TCK TDI TDO TMS TRST GPIO_18/TDM_RCK GPIO_20/TDM_RD GPIO_19/TDM_RFS GPIO_21/TDM_TCK GPIO_23/TDM_TD GPIO_22/TDM_TFS TEST_MODE QUIESCE MPC8314E PowerQUICC Freescale Semiconductor Package Pin Number Pin Type Interrupts AA1 Y5 AA2 AA4 AA5 Configuration JTAG ...

Page 82

... I/O NVDD1 — _OFF I/O NVDD1 — _OFF — — — — — — — — — — — — — — — — — — — — — — — — O NVDD2 — _OFF O NVDD2 — _OFF Freescale Semiconductor ...

Page 83

... PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31] MPC8314E PowerQUICC Freescale Semiconductor Package Pin Number Pin Type J25 J24 K24 H27 H28 H26 G27 G28 F26 F28 G25 F27 E27 E28 D28 ...

Page 84

... NVDD2 — _OFF O NVDD2 — _OFF O NVDD2 — _OFF I/O NVDD2 2 _OFF I/O LVDD1 — _OFF I/O LVDD1 — _OFF I/O LVDD1 3 _OFF I/O LVDD1 — _OFF I/O LVDD1 — _OFF I/O LVDD1 — _OFF I/O LVDD1 — _OFF Freescale Semiconductor ...

Page 85

... GPIO_31/TSEC1_TX_EN/TSEC_TMR_ALARM1 TSEC1_TX_ER/TSEC_TMR_ALARM2 TSEC_GTX_CLK125 TSEC_MDC/LB_POR_CFG_BOOT_ECC TSEC_MDIO GPIO_26/TSEC2_COL GPIO_27/TSEC2_CRS TSEC2_GTX_CLK TSEC2_RX_CLK TSCE2_RX_DV TSEC2_RXD[3] TSEC2_RXD[2] TSEC2_RXD[1] TSEC2_RXD[0] TSEC2_RX_ER TSEC2_TX_CLK TSEC2_TXD[3]/CFG_RESET_SOURCE[0] TSEC2_TXD[2]/CFG_RESET_SOURCE[1] TSEC2_TXD[1]/CFG_RESET_SOURCE[2] TSEC2_TXD[0]/CFG_RESET_SOURCE[3] TSEC2_TX_EN TSEC2_TX_ER MPC8314E PowerQUICC Freescale Semiconductor Package Pin Number Pin Type ETSEC2 A8 E9 B10 B8 C9 C10 D10 ...

Page 86

... O — — I — — I/O USB_VDDA — I/O USB_VDDA — I — — O — — I — — — I — — I — — I — — I — — I — — I — — I/O NVDD1 — _ON I/O NVDD1 — _ON Freescale Semiconductor ...

Page 87

... TGATE2 GPIO_10/USBDR_PCTL0/GTM1_TOUT2/GTM2_TOU T1 GPIO_11/USBDR_PCTL1/GTM1_TOUT4/GTM2_TOU T3 SPIMOSI/GPIO_15 SPIMISO/GPIO_16 SPICLK SPISEL/GPIO_17 GVDD LVDD1 _OFF LVDD2 _ON NVDD1 _OFF NVDD1 _ON NVDD2 _OFF MPC8314E PowerQUICC Freescale Semiconductor Package Pin Number Pin Type SPI Power and Ground Supplies Y11, Y12, Y14, Y15, Y17, AC8, AC11, AC14, AC17, AD6, AD9, AD17, ...

Page 88

... W11, W12, W13, W14, W15, W16, W17, W18, P23, R23, T19, M26, N26, P28, R28, U23, N27 J14, K11, K12, K13, K14, M19 ™ II Pro Processor Hardware Specifications, Rev. 0 Power Notes Supply I — — I — — I — — I — — I — — Freescale Semiconductor ...

Page 89

... Table 66. MPC8314E TEPBGA II Pinout Listing (continued) Signal VSS XCOREVDD XCOREVSS XPADVDD MPC8314E PowerQUICC Freescale Semiconductor Package Pin Number Pin Type A3, A27, B3, B12, B24, B28, C6, C8, C13, C17, C21, C23, C26, D2, D7, D15, D18, D20, D22, E4, E6, E11, E24, E26, F8, F12, F14, F17, F20, G3, ...

Page 90

... LB_POR_CFG_BOOT_ECC is sampled only during the PORESET negation. This pin with an internal pull down resistor enables the ECC by default. To disable the ECC an external strong pull up resistor or a tri-state buffer is needed. MPC8314E PowerQUICC 90 Package Pin Number Pin Type P5, P9, V3 ™ II Pro Processor Hardware Specifications, Rev. 0 Power Notes Supply I — — Freescale Semiconductor ...

Page 91

... Protocol 125-MHz source Converter PCVTR Mux SD_REF_CLK SD_REF_CLK_B + PLL - 125/100 MHz 1 Multiplication factor 1.5, 2, 2.5, and 3. Value is decided by RCWLR[COREPLL]. 2 Multiplication factor and 5. Value is decided by RCWLR[SPMF]. MPC8314E PowerQUICC Freescale Semiconductor Core PLL core_clk TDM DDR memory controller csb_clk ddr_clk 2 lbc_clk x L Clock ...

Page 92

... In addition, some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset. frequency. MPC8314E PowerQUICC 92 Table 67 specifies which units have a configurable clock ™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor ...

Page 93

... PLL VCO Divider). The VCO divider needs to be set properly so that the System PLL VCO frequency is in the range of 450–750 MHz. MPC8314E PowerQUICC Freescale Semiconductor Table 67. Configurable Clock Units Default Frequency csb_clk Off, csb_clk, csb_clk/2, csb_clk/3 ...

Page 94

... II Pro Processor Hardware Specifications, Rev. 0 Input Clock 2 Frequency (MHz) 24 33.33 66.67 133 100 — 96 133 — 120 — — Input Clock 2 frequency (MHz) 25 33.33 66.67 133 100 — 133 — 120 — — Freescale Semiconductor ...

Page 95

... Conf. No. SPMF Core\PLL 1 0100 0000100 2 0100 0000101 MPC8314E PowerQUICC Freescale Semiconductor shows the encodings for RCWL[COREPLL]. COREPLL values that are NOTE Table 72. e300 Core PLL Configuration core_clk : csb_clk Ratio PLL bypassed (PLL off, csb_clk clocks core directly) N/A 1:1 1:1 1.5:1 1 ...

Page 96

... II Pro Processor Hardware Specifications, Rev. 0 133.33 266.66 133.33 333.33 125 312.5 133.33 333.33 125 375 133.33 400 133.33 400 Symbol Value Unit Notes R 23 °C/W θ °C θ °C/W θJMA R 13 °C/W θJMA R 8 °C/W θ °C/W θJC Ψ 6 °C/W JT Freescale Semiconductor ...

Page 97

... When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes. MPC8314E PowerQUICC Freescale Semiconductor ) + P where P DD ...

Page 98

... Because there is not a standard application environment, a standard heat sink is not required. MPC8314E PowerQUICC 98 ) can be used to determine the junction temperature with a JT × θ For instance, the user can change the size of the heat θ CA ™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor ...

Page 99

... Heat sink vendors include the following list: Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com Alpha Novatech 473 Sapena Ct. #12 Santa Clara, CA 95054 Internet: www.alphanovatech.com MPC8314E PowerQUICC Freescale Semiconductor Air Flow Natural Convection 0.5 m/s 1 m/s 2 m/s Natural Convection 0.5 m/s 1 m/s 2 m/s Natural Convection 0 ...

Page 100

... The spring clip should connect to the printed circuit board, either to the board itself, to hooks soldered to the board plastic stiffener. Avoid attachment forces which would MPC8314E PowerQUICC 100 408-436-8770 800-522-6752 603-635-2800 781-935-4850 800-248-2481 888-642-7674 800-347-4572 ™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor ...

Page 101

... PLL Power Supply Filtering Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1,AVDD2 respectively). The AV these voltages are derived directly from VDD through a low frequency filter scheme such as the following. MPC8314E PowerQUICC Freescale Semiconductor + ( θ generates the core clock as a slave to the platform clock ...

Page 102

... MPC8314E PowerQUICC 102 Figure 61, one to each of the AV 10 Ω 2.2 µF 2.2 µF Low ESL Surface Mount Capacitors GND Figure 61. PLL Power Supply Filter Circuit ™ II Pro Processor Hardware Specifications, Rev. 0 pins. By providing DD pin being supplied to minimize DD AV (or L2AV ) DD DD Freescale Semiconductor DD ...

Page 103

... R /V – 1). The drive current is then I term 1 2 Table 76 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD, nominal NVDD, 105°C. MPC8314E PowerQUICC Freescale Semiconductor 2 C). is trimmed until the voltage at the pad equals )/ NVDD R N Pad ...

Page 104

... Table 76. Impedance Characteristics PCI Signals PCI Output Clocks (Not Including PCI (Including Output Clocks) PCI_SYNC_OUT) 25 Target 42 Target 25 Target 42 Target NA Table 105°C. j ™ II Pro Processor Hardware Specifications, Rev. 0 DDR DRAM Symbol 20 Target Target DIFF Freescale Semiconductor Unit Ω Ω Ω ...

Page 105

... PVR = 8085_0020 for all devices and revisions in this table. 27 Document Revision History Table 79 provides a revision history for this hardware specification. Revision Date 0 05/2009 Initial public release. MPC8314E PowerQUICC Freescale Semiconductor Table 77. Part Numbering Nomenclature VR C Temperature Package 3 Range Blank = 0 to 105°C VR – ...

Page 106

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...