A80960JF3V25 Intel, A80960JF3V25 Datasheet
A80960JF3V25
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A80960JF3V25 Summary of contents
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V Embedded 32-Bit Microprocessor Product Features Code Compatible with all 80960Jx Processors High-Performance Embedded Architecture — One Instruction/Clock Execution — Core Clock Rate is: 1x the Bus Clock for 80960JA/JF/JS 2x the Bus Clock for 80960JD/JC 3x the ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com. ...
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Contents 1.0 Introduction.................................................................................................................................... 7 2.0 80960Jx Overview.......................................................................................................................... 9 2.1 80960 Processor Core........................................................................................................ 10 2.2 Burst Bus ............................................................................................................................11 2.3 Timer Unit ...........................................................................................................................11 2.4 Priority Interrupt Controller..................................................................................................11 2.5 Instruction Set Summary ....................................................................................................12 2.6 Faults and Debugging.........................................................................................................12 2.7 Low Power Operation ......................................................................................................... 12 ...
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Contents Figures 1 80960Jx Microprocessor Package Options .................................................................................. 7 2 80960Jx Block Diagram.............................................................................................................. 10 3 132-Lead Pin Grid Array Top View-Pins Facing Down............................................................... 23 4 132-Lead Pin Grid Array Bottom View-Pins Facing Up .............................................................. 24 5 132-Lead PQFP - Top ...
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HOLD/HOLDA Waveform For Bus Arbitration ............................................................................75 49 Cold Reset Waveform.................................................................................................................76 50 Warm Reset Waveform ..............................................................................................................77 51 Entering the ONCE State............................................................................................................78 52 Bus States with Arbitration..........................................................................................................80 53 Summary of Aligned and Unaligned Accesses (32-Bit Bus).......................................................84 54 Summary of Aligned and ...
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Contents 42 Boundary-Scan Register—Bit Order .......................................................................................... 81 43 Natural Boundaries for Load and Store Accesses...................................................................... 81 44 Summary of Byte Load and Store Accesses .............................................................................. 82 45 Summary of Short Word Load and Store Accesses ................................................................... 82 46 Summary of ...
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... Introduction This document contains information for the 80960Jx microprocessors, including electrical characteristics and package pinout information. Detailed functional descriptions, other than parametric performance, are published in the i960 (272483) and may be viewed online at http://developer.intel.com/design/i960/Techinfo/80960JX/. Figure 1. 80960Jx Microprocessor Package Options i x80960JX XXXXXXXXSS © ...
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V Embedded 32-Bit Microprocessor This page intentionally left blank. 8 Datasheet ...
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Overview The 80960Jx processor offers high performance to cost-sensitive 32-bit embedded applications. The 80960Jx is object code compatible with the 80960 core architecture and is capable of sustained execution at the rate of one instruction per clock. This ...
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... Independent 32-Bit SRC1, SRC2, and DEST Buses 2.1 80960 Processor Core The 80960Jx family is a scalar implementation of the 80960 core architecture. Intel designed this processor core as a very high performance device that is also cost-effective. Factors that contribute to the core’s performance include: • ...
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Burst Bus A 32-bit high-performance Bus Controller Unit (BCU) interfaces the 80960Jx to external memory and peripherals. The BCU fetches instructions and transfers data at the rate four 32-bit words per six clock cycles. The external ...
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... Low Power Operation Intel fabricates the 80960Jx using an advanced sub-micron manufacturing process. The processor’s sub-micron topology provides the circuit density for optimal cache size and high operating speeds while dissipating modest power. The processor also uses dynamic power management to turn off clocks to unused circuits ...
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The 80960Jx provides testability features compatible with IEEE Standard Test Access Port and Boundary Scan Architecture (IEEE Std. 1149.1). One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins (ONCE mode). ONCE mode may ...
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V Embedded 32-Bit Microprocessor Table 2. 80960Jx Instruction Set Data Movement Load Store Move † Conditional Select Load Address Comparison Compare Conditional Compare Compare and Increment Compare and Decrement Test Condition Code Check Bit Debug Modify Trace Controls ...
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Packaging Information 3.1 Available Processors and Packages The 80960Jx is offered in various speed grades and three package types. The 132-pin Pin Grid Array (PGA) device is specified for operation case temperature range of 0° C ...
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... For pinout diagrams of the PQFP package, see on page 30. For additional package specifications and information, refer to the Intel Packaging Databook, available in individual chapters, at http://www.intel.com. NOTE: To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x". ...
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Table 7. Pin Description Nomenclature Symbol I Input pin only. O Output pin only. I/O Pin may be either an input or output. – Pin must be connected as described. Synchronous. Inputs must meet setup and hold times relative to ...
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V Embedded 32-Bit Microprocessor Table 8. Pin Description—External Bus Signals (Sheet NAME TYPE I/O S(L) AD[31:0] R(X) H(Z) P(Q) O R(0) ALE H(Z) P(0) O R(1) ALE# H(Z) P(1) O R(1) ADS# H(Z) P(1) O ...
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Table 8. Pin Description—External Bus Signals (Sheet NAME TYPE O R(1) BE[3:0]# H(Z) P(1) O WIDTH/ R(0) HLTD[1:0] H(Z) P(1) O R(X) D/C# H(Z) P(Q) O R(0) W/R# H(Z) P(Q) O R(0) DT/R# H(Z) P(Q) Datasheet 80960JA/JF/JD/JS/JC/JT ...
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V Embedded 32-Bit Microprocessor Table 8. Pin Description—External Bus Signals (Sheet NAME TYPE O R(1) DEN# H(Z) P(1) O R(1) BLAST# H(Z) P(1) I RDYRCV# S(L) I/O S(L) LOCK#/ R(H) ONCE# H(Z) P(1) I HOLD ...
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Table 8. Pin Description—External Bus Signals (Sheet NAME TYPE O R(Q) HOLDA H(1) P(Q) O R(0) BSTAT H(Q) P(0) Table 9. Pin Description—Processor Control Signals, Test Signals, and Power (Sheet NAME TYPE CLKIN I ...
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V Embedded 32-Bit Microprocessor Table 9. Pin Description—Processor Control Signals, Test Signals, and Power (Sheet NAME TYPE O R(Q) TDO HQ) P(Q) I TRST# A(L) I TMS S(L) V – CC VCCPLL – VCC5 – ...
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PGA Pinout Figure 3. 132-Lead Pin Grid Array Top View-Pins Facing Down AD6 AD11 AD13 N AD3 AD7 AD10 M AD0 AD4 L V AD1 ...
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V Embedded 32-Bit Microprocessor Figure 4. 132-Lead Pin Grid Array Bottom View-Pins Facing AD22 AD25 N AD26 AD27 M AD30 AD29 L BE2# BE3 ...
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Table 11. 132-Lead PGA Pinout—In Signal Order Signal Pin AD0 M14 AD1 L13 AD2 K12 AD3 N14 AD4 M13 AD5 L12 AD6 P14 AD7 N13 AD8 M12 AD9 M11 AD10 N12 AD11 P13 AD12 M10 AD13 ...
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V Embedded 32-Bit Microprocessor Table 12. 132-Lead PGA Pinout—In Pin Order Pin Signal A1 ADS# A2 WIDTH/HLTD1 A3 ALE A10 NMI# A11 ...
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PQFP Pinout Figure 5. 132-Lead PQFP - Top View TRST# 1 TCK 2 TMS 3 HOLD 4 XINT0# 5 XINT1# 6 XINT2# 7 XINT3 (I/ (I/ XINT4# 12 XINT5# ...
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V Embedded 32-Bit Microprocessor Table 13. 132-Lead PQFP Pinout—In Signal Order Signal Pin AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 100 ...
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Table 14. 132-Lead PQFP Pinout—In Pin Order Pin Signal 1 TRST# 2 TCK 3 TMS 4 HOLD 5 XINT0# 6 XINT1# 7 XINT2# 8 XINT3 (I/ (I/ XINT4# 12 XINT5# 13 XINT6# 14 ...
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V Embedded 32-Bit Microprocessor 3.2.4 80960Jx 196-Ball MPBGA Pinout Figure 6. 196-Ball Mini Plastic Ball Grid Array Top View-Balls Facing Down 1 A AD28 NC B AD30 AD31 ...
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Figure 7. 196-Ball Mini Plastic Ball Grid Array Bottom View-Balls Facing AD8 B AD4 AD7 C AD2 AD6 D AD1 AD0 VCCPLL CLKIN H NC ...
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V Embedded 32-Bit Microprocessor Table 15. 196-Ball MPBGA Pinout—In Signal Order (Sheet Signal Pin A2 A3 AD0 D13 AD1 D14 AD2 C14 AD3 D11 AD4 B14 AD5 D12 AD6 C13 AD7 B13 AD8 A13 AD9 ...
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Table 15. 196-Ball MPBGA Pinout—In Signal Order (Sheet Signal Pin VSS G7 VSS G8 VSS G9 VSS G10 VSS G11 VSS H4 VSS H5 VSS H6 VSS H7 VSS H8 VSS H9 VSS H10 NOTE: Do not ...
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V Embedded 32-Bit Microprocessor Table 16. 196-Ball MPBGA Pinout—In Pin Order (Sheet Pin Signal B7 AD20 B8 AD17 B9 AD14 B10 AD12 B11 AD10 B12 AD9 B13 AD7 B14 AD4 AD31 C3 ...
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... This document contains information on products in the production phase of development. The specifications within this datasheet are subject to change without prior notice. Verify with your local Intel sales office or the world wide web to ensure that you have the latest datasheet and device specification update before finalizing a design. ...
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... Place liberal decoupling capacitance near the 80960Jx, since the processor may cause transient power surges. The 80960JS/JC/JT processors are produced on Intel’s advanced CMOS process. Proper bulk decoupling must be used to prevent device damage during initial power up and during transitions from low power mode to normal processor operation ...
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When the regulator cannot prevent the 2.25 V differential, the addition of the resistor is a simple and reliable method for limiting current. The resistor may also prevent damage in the case of a power failure, where the 5 V ...
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V Embedded 32-Bit Microprocessor 4.6 D.C. Specifications Table 20. 80960Jx D.C. Characteristics Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V Output Ground Bounce ...
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Table 21. 80960Jx I Characteristics (Sheet Symbol I LI1 I LI2 Active CC (Power Supply) I Active CC (Thermal) Datasheet 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor Parameter Input Leakage Current for ...
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V Embedded 32-Bit Microprocessor Table 21. 80960Jx I Characteristics (Sheet Symbol I Test CC (Power modes) 40 Parameter Reset mode 80960JT-100 80960JC-66 80960JC-50 80960JS-33 80960JS-25 80960JD-66 80960JD-50 80960JD-40 80960JD-33 80960JA/JF-33 80960JA/JF-25 80960JA-16 Halt mode ...
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Table 21. 80960Jx I Characteristics (Sheet Symbol ICC5 Current on the VCC5 Pin NOTES: 1. These pins have internal pullup devices. Typical leakage current is not tested. 2. Measured with device operating and outputs loaded to ...
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V Embedded 32-Bit Microprocessor 4.7 A.C. Specifications The 80960Jx A.C. timings are based upon device characterization. Table 22. 80960Jx A.C. Characteristics (Sheet Symbol CLKIN Frequency 80960JT-100 80960JC-66 80960JC-50 80960JS-33 80960JS- 80960JD-66 80960JD-50 80960JD-40 ...
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Table 22. 80960Jx A.C. Characteristics (Sheet Symbol Output Valid Delay, Except ALE/ALE# Inactive and DT/R# for 3.3 V input signals Same as above, but for 5.5 V input signals T OV1 Extended Temp MPBGA and PQFP (JS/JC/JT ...
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V Embedded 32-Bit Microprocessor Table 22. 80960Jx A.C. Characteristics (Sheet Symbol Input Hold from RESET# — ONCE#, STEST T 80960JS/JC/JT IH4 80960JD 80960JA/JF Address Valid to ALE/ALE# Inactive T For 3.3 V Data Input Signals ...
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Table 23. Note Definitions for Table 22, 80960Jx AC Characteristics NOTES: 1. Not tested ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter frequency spectrum should not have any power ...
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V Embedded 32-Bit Microprocessor 4.7.1.1 Output Delay or Hold vs. Load Capacitance Figure 11. Output Delay or Hold vs. Load Capacitance–80960JS/JC/JT (3.3 V Signals) Figure 12. Output Delay or Hold vs. Load Capacitance–80960JS/JC/ Signals ...
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Figure 13. Output Delay or Hold vs. Load Capacitance–80960JA/JF/JD nom + 8 nom + 7 nom + 6 nom + 5 nom + 4 nom + 3 nom + 2 nom + 1 nom + 0 Rise and Fall times ...
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V Embedded 32-Bit Microprocessor Note: The T Derating curve applies only when an imbalance in the capacitive load occurs between the LX AD bus and ALE. The T and ALE#. Figure 15. T vs. AD Bus Load Capacitance–80960JS/JC/JT ...
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Note: The T Derating curve applies only when an imbalance in the capacitive load occurs between the LX AD bus and ALE. The T and ALE#. 4.7.1.3 ICC Active vs. Frequency Figure 17. I Active (Power Supply) vs. Frequency–80960JA/JF CC ...
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V Embedded 32-Bit Microprocessor Figure 19. 80960JD I Active (Power Supply) vs. Frequency CC 600 500 400 300 200 100 Figure 20. 80960JD I Active (Thermal) vs. Frequency CC 600 500 400 300 200 100 ...
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Figure 21. 80960JC I Active (Power Supply) vs. Frequency CC 400 350 300 250 200 150 100 50 0 Figure 22. 80960JC I Active (Thermal) vs. Frequency CC 400 350 300 250 200 150 100 Datasheet 80960JA/JF/JD/JS/JC/JT ...
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V Embedded 32-Bit Microprocessor Figure 23. 80960JS I Active (Power Supply) vs. Frequency CC 300 250 200 150 100 Figure 24. 80960JS I Active (Thermal) vs. Frequency CC 250 200 150 100 Icc Active ...
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A.C. Timing Waveforms Figure 25. CLKIN Waveform T CR Figure 26. T Output Delay Waveform OV1 WIDTH/HLTD[1:0], D/C#, W/R#, DEN#, HOLDA, BSTAT, FAIL# Datasheet 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor 1.5 ...
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V Embedded 32-Bit Microprocessor Figure 27. T Output Float Waveform OF DEN#, BLAST#, LOCK# Figure 28. T and T Input Setup and Hold Waveform IS1 IH1 AD[31:0] XINT[7:0]# Figure 29. T and T Input Setup and Hold Waveform ...
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Figure 30. T and T Input Setup and Hold Waveform IS3 IH3 CLKIN RESET# Figure 31. T and T Input Setup and Hold Waveform IS4 IH4 RESET# ONCE#, STEST Datasheet 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor 1 ...
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V Embedded 32-Bit Microprocessor Figure 32 and T LX LXL LXA CLKIN AD[31:0] Figure 33. DT/R# and DEN# Timings Waveform CLKIN DT/R# DEN# 56 Relative Timings Waveform LXL ALE 1.5 ...
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Figure 34. TCK Waveform T BSCR Figure 35. T and T BSIS1 BSIH1 TCK TMS TDI Figure 36. T and T BSOV1 BSOF1 TCK TDO Datasheet 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor T BSCF T BSCH T BSCL Input Setup ...
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V Embedded 32-Bit Microprocessor Figure 37. T and T BSOV2 BSOF2 TCK Non-Test Outputs Figure 38. T and T BSIS2 BSIH2 TCK Non-Test Inputs 58 Output Delay and Output Float Waveform 1 BSOV2 Valid ...
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Device Identification 80960Jx processors may be identified electrically, according to device type and stepping (see Figure 39, and Table 25 for all 5 V, 80960Jx processors V-tolerant 80960Jx processors. The device ID was enhanced to differentiate between ...
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... Product Type (Indicates i960 CPU) Generation Type 0001 = J-series D DPCC D = Clock Multiplier Model (P) Product Derivative C = Cache Size 000 0000 1001 Manufacturer ID (Indicates Intel) Table 26. 80960JS/JC/JT Device ID Model Types Device 80960JT A0, A1 80960JC A1 80960JS A1 60 Part Number Product V Type Gen ...
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... J-series D000C D = Clock Doubled (0) Not Clock-Doubled Model (1) Clock Doubled C = Cache Size (0) 4K I-cache, 2K D-cache (1) 2K I-cache, 1K D-cache 000 0000 1001 Manufacturer ID (Indicates Intel) Table 28. 80960JD Device ID Model Types Device 80960JD C0 Datasheet 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor Part Number Product V Type Gen ...
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... Field Version See 0 = 3.3 V device device 00 0100 Product Type (Indicates i960 CPU) Generation Type 0001 = J-series 0000C C = Cache Size Model 000 0000 1001 Manufacturer ID (Indicates Intel) Table 30. 80960JA/JF Device ID Model Types Device 80960JA C0 80960JF C0 62 Part Number Product V Type Gen Model ...
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Thermal Specifications The 80960Jx is specified for operation when T 100° C for PGA, MPBGA and PQFP packages. Extended temperature devices are also available in a PQFP package and an MPBGA package with T measured in any environment to ...
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V Embedded 32-Bit Microprocessor Table 33. 132-Lead PGA Package Thermal Characteristics Parameter (Junction-to-Case) JC (Case-to-Ambient) (No Heatsink) CA (Case-to-Ambient) (Omnidirectional Heatsink) CA (Case-to-Ambient) (Unidirectional Heatsink) CA NOTES: 1. This table applies to a PGA device plugged into a ...
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Table 35. 80960JS/JC/JT 196-Ball MPBGA Package Thermal Characteristics Parameter (Junction-to-Case) JC (Case-to-Ambient) (No Heatsink) CA NOTES: 1. This table applies to an MPBGA device soldered directly into a board with all Table 36. ...
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V Embedded 32-Bit Microprocessor Table 37. Maximum T at Various Airflows in °C (80960JT) A PQFP T without Heatsink A Package T without Heatsink A T with Omnidirectional A PGA Heatsink Package T with Unidirectional A Heatsink MPBGA ...
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Table 39. Maximum T at Various Airflows in °C (80960JD) A PQFP T without Heatsink A Package T without Heatsink A PGA T with Omnidirectional A 1 Package Heatsink T with Unidirectional A 2 Heatsink MPBGA T without Heatsink A ...
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V Embedded 32-Bit Microprocessor Table 41. Maximum T at Various Airflows in °C (80960JA/JF) A For x80960JA/JF T without Heatsink PQFP A Package For x80960JA-25 T without Heatsink A T without Heatsink A PGA T with Omnidirectional A ...
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Bus Functional Waveforms Figure 42 through Figure 47 arbitration sequence. applied to the device. operation. Figure 51 the device. Figure 53 summarize all possible combinations of bus accesses across 8-, 16-, and 32-bit buses according to data alignment. Figure ...
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V Embedded 32-Bit Microprocessor Figure 43. Burst Read and Write Transactions Without Wait States, 32-Bit Bus CLKIN AD31:0 ADS# BE3:0# WIDTH1:0 BLAST# DT/R# DEN# RDYRCV ...
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Figure 44. Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus CLKIN AD31:0 ALE ADS# A3:2 BE3:0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# RDYRCV# Datasheet 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor ...
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V Embedded 32-Bit Microprocessor Figure 45. Burst Read and Write Transactions Without Wait States, 8-Bit Bus CLKIN AD31:0 ALE ADS# A3:2 BE1#/A1 BE0#/A0 WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# RDYRCV ...
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Figure 46. Burst Read and Write Transactions With 1, 0 Wait States and Extra Tr State on Read, 16-Bit Bus CLKIN AD31:0 ALE ADS# A3:2 BE1#/A1 BE3#/BHE BE0#/BLE WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# RDYRCV# Datasheet 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded ...
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V Embedded 32-Bit Microprocessor Figure 47. Double Word Read Bus Request, Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian CLKIN AD31:0 ALE ADS# A3:2 BE3:0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# RDYRCV ...
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Figure 48. HOLD/HOLDA Waveform For Bus Arbitration CLKIN Outputs: AD31:0, ALE, ALE#, ADS#, A3:2, BE3:0#, WIDTH/HLTD1:0, D/C#, W/R#, DT/R#, DEN#, BLAST#, LOCK# HOLD HOLDA NOTE: HOLD is sampled on the rising edge of CLKIN. The processor asserts HOLDA to grant ...
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CLKIN V CC ALE#, ADS#, BE3:0#, DEN#, BLAST# ALE#,W/R#, DT/R# WIDTH/HLTD1:0 FAIL# AD31:0, A3:2,D/C# HOLD HOLDA LOCK#/ ONCE# STEST RESET# Notes: 1. The processor asserts FAIL# during built-in self-test. When self- test passes, the FAIL# pin is deasserted.The processor also ...
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CLKIN ALE#, ADS#, BE3:0#, DEN#, BLAST# ALE, W/R#,DT/R#, BSTAT, WIDTH/HLTD1:0 FAIL# AD31:0, A3:2, D/C# HOLD HOLDA LOCK#/ONCE# STEST Maximum RESET# Low to Reset State RESET# Valid 4 CLKIN Cycles RESET# High to First Bus Activity: (CLKIN cycles) Minimum RESET# Low ...
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CLKIN V CC ALE#, ADS#, BE3:0#, DEN#, BLAST# ALE,W/R,# DT/R#, WIDTH/HLTD1:0 FAIL# AD31:0, A3:2, D/C# HOLD HOLDA LOCK#/ ONCE# STEST RESET# NOTES: 1. ONCE# mode may be entered prior to the rising edge of RESET#: ONCE# input is not latched ...
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Basic Bus States The bus has five basic bus states: idle (Ti), address (Ta), wait/data (Tw/Td), recovery (Tr), and hold (Th). During system operation, the processor continuously enters and exits different bus states. Figure 52 shows the five bus ...
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V Embedded 32-Bit Microprocessor Figure 52. Bus States with Arbitration REQUEST PENDING AND (NO HOLD OR LOCKED) NO REQUEST AND (NO HOLD OR LOCKED) ONCE & RESET DEASSERTION RESET To Ti — IDLE STATE Ta — ADDRESS STATE ...
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Table 42. Boundary-Scan Register—Bit Order Bit Signal RDYRCV# 0 (TDI) 1 HOLD 2 XINT0# 3 XINT1# 4 XINT2# 5 XINT3# 6 XINT4# 7 XINT5# 8 XINT6# 9 XINT7# 10 NMI# 11 FAIL# 12 ALE# 13 WIDTH/HLTD1 14 WIDTH/HLTD0 15 A2 ...
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V Embedded 32-Bit Microprocessor Table 44. Summary of Byte Load and Store Accesses Address Offset from Natural Boundary (in Bytes) +0 (aligned) Table 45. Summary of Short Word Load and Store Accesses Address Offset from Natural Boundary (in ...
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Table 46. Summary of n-Word Load and Store Accesses ( Address Offset from Natural Boundary in Bytes +0 (aligned ...
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V Embedded 32-Bit Microprocessor Figure 53. Summary of Aligned and Unaligned Accesses (32-Bit Bus) Byte Offset Word Offset Short-Word Load/Store Word Load/Store Double-Word Load/Store Short Access (Aligned) Byte, Byte ...
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Figure 54. Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) 0 Byte Offset 0 Word Offset Triple-Word Load/Store Quad-Word Load/Store Datasheet 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor One Three-Word Burst (Aligned) Byte, Short, ...
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V Embedded 32-Bit Microprocessor This page intentionally left blank. 86 Datasheet ...