A80960HD80SL2GK Intel, A80960HD80SL2GK Datasheet

IC I960HD 3.3V 80MHZ 168CPGA

A80960HD80SL2GK

Manufacturer Part Number
A80960HD80SL2GK
Description
IC I960HD 3.3V 80MHZ 168CPGA
Manufacturer
Intel
Datasheet

Specifications of A80960HD80SL2GK

Rohs Status
RoHS non-compliant
Processor Type
i960
Features
HD suffix, 32-Bit, 40MHz Bus
Speed
80MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
168-CPGA
Other names
815177
80960HA/HD/HT 32-Bit High-Performance
Superscalar Processor
Product Features
32-Bit Parallel Architecture
Processor Core Clock
Binary Compatible with Other 80960
Processors
Issue Up To 150 Million Instructions per
Second
High-Performance On-Chip Storage
Separate 128-Bit Internal Paths For
Instructions/Data
— Load/Store Architecture
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers
— 1.28 Gbyte Internal Bandwidth
— On-Chip Register Cache
— 80960HA is 1x Bus Clock
— 80960HD is 2x Bus Clock
— 80960HT is 3x Bus Clock
— 16 Kbyte Four-Way Set-Associative
— 8 Kbyte Four-Way Set-Associative Data
— 2 Kbyte General Purpose RAM
(80 MHz)
Instruction Cache
Cache
3.3 V Supply Voltage
Guarded Memory Unit
32-Bit Demultiplexed Burst Bus
High-Speed Interrupt Controller
Dual On-Chip 32-Bit Timers
— 5 V Tolerant Inputs
— TTL Compatible Outputs
— Provides Memory Protection
— User/Supervisor Read/Write/Execute
— Per-Byte Parity Generation/Checking
— Address Pipelining Option
— Fully Programmable Wait State Generator
— Supports 8-, 16- or 32-Bit Bus Widths
— 160 Mbyte/s External Bandwidth
— Up to 240 External Interrupts
— 31 Fully Programmable Priorities
— Separate, Non-maskable Interrupt Pin
— Auto Reload Capability and One-Shot
— CLKIN Prescaling, divided by 1, 2, 4 or 8
— JTAG Support - IEEE 1149.1 Compliant
(40 MHz)
Order Number: 272495-009
Datasheet
August 2004

Related parts for A80960HD80SL2GK

A80960HD80SL2GK Summary of contents

Page 1

High-Performance Superscalar Processor Product Features 32-Bit Parallel Architecture — Load/Store Architecture — Sixteen 32-Bit Global Registers — Sixteen 32-Bit Local Registers — 1.28 Gbyte Internal Bandwidth (80 MHz) — On-Chip Register Cache Processor Core Clock — 80960HA is ...

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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com. ...

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... Contents 1.0 About This Document ................................................................................................................... 9 2.0 Intel 80960Hx Processor ............................................................................................................... 9 ® 2.1 The i960 Processor Family ...............................................................................................10 2.2 Key 80960Hx Features .......................................................................................................10 2.2.1 Execution Architecture ...........................................................................................10 2.2.2 Pipelined, Burst Bus ..............................................................................................10 2.2.3 On-Chip Caches and Data RAM............................................................................11 2.2.4 Priority Interrupt Controller.....................................................................................11 2.2.5 Guarded Memory Unit ...........................................................................................11 2.2.6 Dual Programmable Timers ...

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Contents 7 VCC5 Current-Limiting Resistor ................................................................................................. Test Load.............................................................................................................................. 45 9 CLKIN Waveform........................................................................................................................ 46 10 Output Delay Waveform ............................................................................................................. 46 11 Output Delay Waveform ............................................................................................................. 46 12 Output Float Waveform .............................................................................................................. 47 13 Input Setup and Hold Waveform ...

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A Summary of Aligned and Unaligned Transfers for 8-Bit Bus...................................................81 58 Idle Bus Operation ......................................................................................................................82 59 Bus States ..................................................................................................................................83 Tables 1 80960Hx Product Description ....................................................................................................... 9 2 Fail Codes For BIST (bit ...................................................................................................12 3 Remaining Fail ...

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Contents Revision History Date August 2004 September 2002 July 1998 6 Revision To address the fact that many of the package prefix variables have 009 changed, all package prefix variables in this document are now indicated with an "x". Formatted ...

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Date July 1998 (continued) (continued) August 1997 Datasheet Revision In Table 23 “80960Hx AC Characteristics” on page • Added overbars where required. • Modified T to list separate specifications for 3.3 V and 5 V. DVNH • Modified T , ...

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Contents This page intentionally left blank. 8 Datasheet ...

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... RISC-style, embedded processors allows customers to create scalable designs that meet multiple price and performance points. This is accomplished by providing processors that may run at the bus speed or faster using Intel’s clock multiplying technology (see Table 1). The 80960Hx core is capable of issuing 150 million instructions per second, using a sophisticated instruction scheduler that allows the processor to sustain a throughput of two instructions every core clock, with a peak performance of three instructions per clock ...

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... Processor Family ® The i960 processor family is a 32-bit RISC architecture created by Intel to serve the needs of embedded applications. The embedded market includes applications as diverse as industrial automation, avionics, image processing, graphics and communications. Because all members of the i960 processor family share a common core architecture, i960 applications are code-compatible ...

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To reduce the effect of wait states, the bus design is decoupled from the core. This lets the processor execute instructions while the bus performs memory accesses independently. The Bus Controller’s key features include: • ...

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Dual Programmable Timers The processor provides two independent 32-bit timers, with four programmable clock rates. The user configures the timers through the Timer Unit registers. These registers are memory-mapped within the 80960Hx, addressable on 32-bit boundaries. The timers ...

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Instruction Set Summary Table 4 summarizes the 80960Hx instruction set by logical groupings. Table 4. 80960Hx Instruction Set Data Movement Load Store Move Load Address 2 Conditional Select Comparison Compare Conditional Compare Compare and Increment Compare and Decrement 2 ...

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... This section describes the pins, pinouts and thermal characteristics for the 80960Hx in the 168-pin ceramic Pin Grid Array (PGA) package, 208-pin PowerQuad2* (PQ4). For complete package specifications and information, see the Intel Packaging Handbook (Order# 240800). The 80960HA/HD/HT is offered with eight speeds and two package types ...

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Pin Descriptions This section defines the 80960Hx pins. descriptions in Table which may be driven active according to normal JTAG specifications. Table 6. Pin Description Nomenclature Symbol I Input only pin. O Output only pin. I/O Pin may be ...

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Table 7. 80960Hx Processor Family Pin Descriptions (Sheet Name Type O H(Z) A31:2 B(Z) R(Z) I/O S(L) D31:0 H(Z) B(Z) R(Z) I/O S(L) DP3:0 H(Z) B(Z) R(Z) O H(Q) PCHK B(Q) R(1) O H(Z) BE3:0 B(Z) ...

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Table 7. 80960Hx Processor Family Pin Descriptions (Sheet Name Type O H(Z) SUP B(Z) R(1) O H(Z) ADS B(Z) R(1) I READY S(L) I BTERM S(L) O H(Z) WAIT B(Z) R(1) O H(Z) BLAST B(Z) R(1) O ...

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Table 7. 80960Hx Processor Family Pin Descriptions (Sheet Name Type I HOLD S(L) O H(1) HOLDA B(0) R(Q) I BOFF S(L) O H(Q) BREQ B(Q) R(0) O H(Q) BSTALL B(Q) R(0) O H(Z) CT3:0 B(Z) R(Z) ...

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Table 7. 80960Hx Processor Family Pin Descriptions (Sheet Name Type CLKIN I I RESET A(L) I STEST S(L) O H(Q) FAIL B(Q) R(0) ONCE I TCK I TDI I TDO O TRST I TMS I VCC5 I ...

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Mechanical Data 3.2.1 80960Hx PGA Pinout Figure 2 depicts the complete 80960Hx PGA pinout as viewed from the top side of the component (i.e., pins facing down). pin-side of the package (i.e., pins facing up). location. See ...

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Figure 3. 80960Hx 168-Pin PGA Pinout—View from Bottom (Pins Facing Up BOFF SS 2 FAIL STEST 3 DP0 DP1 4 DP2 DP3 5 VOLDET TCK 6 TRST TMS 7 TDI TDO PCHK 9 ...

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Table 8. 80960Hx 168-Pin PGA Pinout—Signal Name Order (Sheet PGA Signal Name Pin A2 D16 A3 D17 A4 E16 A5 E17 A6 F17 A7 G16 A8 G17 A9 H17 A10 J17 A11 K17 A12 L17 A13 ...

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Table 8. 80960Hx 168-Pin PGA Pinout—Signal Name Order (Sheet PGA Signal Name Pin V J16 K16 M16 N15 ...

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Table 9. 80960Hx 168-Pin PGA Pinout—Pin Number Order (Sheet PGA Signal Name Pin FAIL A3 DP0 A4 DP2 A5 VOLDET A6 TRST A7 TDI A8 TDO A9 NC A10 NC A11 CT0 ...

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Table 9. 80960Hx 168-Pin PGA Pinout—Pin Number Order (Sheet PGA Signal Name Pin Q4 D28 Q5 D30 Q10 V SS Q11 V SS Q12 SUP ...

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PQ4 Pinout Figure 4. 80960Hx 208-Pin PQ4 Pinout PIN 156 PIN 157 NMI XINT7 XINT6 XINT5 XINT4 XINT3 XINT2 XINT1 XINT0 ...

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Table 10. 80960Hx PQ4 Pinout—Signal Name Order (Sheet PQ4 Signal Name Pin A2 151 A3 150 A4 147 A5 146 A6 145 A7 144 A8 141 A9 140 A10 139 A11 138 A12 135 A13 134 A14 ...

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Table 10. 80960Hx PQ4 Pinout—Signal Name Order (Sheet PQ4 Signal Name Pin 101 CC V 102 CC V 109 CC V 115 CC V 117 CC V 123 CC V 128 ...

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Table 11. 80960Hx PQ4 Pinout—Pin Number Order (Sheet PQ4 Signal Name Pin FAIL 6 ONCE ...

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Table 11. 80960Hx PQ4 Pinout—Pin Number Order (Sheet PQ4 Signal Name Pin 121 A20 122 V SS 123 V CC 124 A19 125 A18 126 A17 127 A16 128 V CC 129 V SS 130 V ...

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Package Thermal Specifications The 80960Hx is specified for operation when T 0 ° °C. T may be measured in any environment to determine whether the 80960Hx is C within the specified operating range. Measure the case temperature ...

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Table 12. Maximum T at Various Airflows in °C (PGA Package Only with A Heatsink Core 1X Bus T Clock A without Heatsink T with A Heatsink Core 2X Bus Clock T A without Heatsink T with ...

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Table 14. Maximum T at Various Airflows in °C (PQ4 Package Only with A † Heatsink Core 1X Bus T Clock A without Heatsink T with A † Heatsink Core 2X Bus Clock T A without Heatsink T ...

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... Heat Sink Adhesives Intel recommends silicone-based adhesives to attach heat sinks to the PGA package. There is no particular recommendation concerning the PQ4 package. 3.5 PowerQuad4 Plastic Package The 80960Hx family is available in an improved version of the common 208-lead SQFP plastic package called the PowerQuad4* (PQ4). The PQ4 package dimensions and lead pitch are identical to the SQFP package and the former PQ2 package, so the PQ4 fits into the same board footprint ...

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... See 3.3 V device CC 00 0100 Product Type (Indicates i960 CPU) Generation Type 0010 = H-series Model See 000 0000 1001 Manufacturer ID (Indicates Intel) Table 17. 80960Hx Device ID Model Types Device 80960HA 80960HD See 80960HT Table 18. Device ID Version Numbers for Different Steppings Stepping B0, B2 NOTE: This data sheet applies to the B2 stepping ...

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Sources for Accessories The following is a list of suggested sources for 80960Hx accessories. This is neither an endorsement nor a warranty of the performance of any of the listed products and/or companies. Sockets • 3M Textool Test ...

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Electrical Specifications 4.1 Absolute Maximum Ratings Table 19. Absolute Maximum Ratings Parameter Storage Temperature Case Temperature Under Bias Supply Voltage with respect to V Voltage on VCC5 with respect to V Voltage on Other Pins with respect to V ...

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Recommended Connections Power and ground connections must be made to multiple V 80960Hx-based circuit board should include power (V distribution. Every V connected to the ground plane. Pins identified as “NC” —no connect pins—must not be connected in ...

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Table 21. V Specification for Dual Power Supply Requirements (3 DIFF Sym Parameter VCC5 DIFF Difference 4.5 VCCPLL Pin Requirements When the voltage on the VCCPLL power supply pin exceeds the V time, including the ...

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D.C. Sp ecifications Table 22. 80960Hx D.C. Characteristics (Sheet Per the conditions described in Symbol V Input Low Voltage IL V Input High Voltage IH Output Low Voltage V OL All outputs except FAIL V ...

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Table 22. 80960Hx D.C. Characteristics (Sheet Per the conditions described in Symbol I CC5 Current on the VCC5 Pin Input Capacitance for Output Capacitance of each C OUT output pin C I/O Pin Capacitance I/O ...

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A.C. Specifications Table 23. 80960Hx A.C. Characteristics (Sheet Per conditions in Section 4.2, “Operating Conditions” on page 37 Symbol CLKIN Frequency T F 80960HD CLKIN Period 80960HA T 80960HD CLKIN Period Stability T CS CLKIN ...

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Table 23. 80960Hx A.C. Characteristics (Sheet Per conditions in Section 4.2, “Operating Conditions” on page 37 Symbol Input Setup for T IS2 BOFF Input Hold for T IH2 BOFF A31:2 Valid to ADS Rising T AVSH1 BE3:0, ...

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Table 24. A.C. Characteristics Notes NOTES: 1. See Section 4.8, “AC Timing Waveforms” on page 46 2. See Figure 25, “Output Delay or Hold vs. Load Capacitance” on page 52 for output delays and hold times. 3. See Figure ...

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A.C. Test Conditions A.C. values are derived using the 50 pF load shown in Load Capacitance” on page (except for CLKIN) are assumed to have a rise and fall time from 0 2.0 V. ...

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A.C. Timing Waveforms Figure 9. CLKIN Waveform T CR Figure 10. Output Delay Waveform A31:2, D31:0 write only, DP3:0 write only PCHK, BE3:0, W/R, D/C, SUP, ADS, DEN, LOCK, HOLDA, BREQ, BSTALL, CT3:0, FAIL, WAIT, BLAST Figure 11. ...

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Figure 12. Output Float Waveform A31:2, D31:0 write only, DP3:0 write only PCHK, BE3:0, W/R, D/C, SUP, ADS, DEN, LOCK, HOLDA, CT3:0, WAIT, BLAST, DT/R Figure 13. Input Setup and Hold Waveform READY, HOLD, BTERM, BOFF, D31:0 on reads, DP3:0 ...

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Figure 15. Hold Acknowledge Timings CLKIN HOLDA T T — OUTPUT DELAY - The maximum output delay is referred to as the Output Valid Delay ( The minimum output delay is referred to as the Output Hold ...

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Figure 17. TCK Waveform Figure 18. Input Setup and Hold Waveforms for T TCLK Inputs: TMS TDI Datasheet T T BSCR BSCF T BSCH T T BSC and T BSIS1 1 BSIH1 T BSIS1 Valid 1.5 ...

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Figure 19. Output Delay and Output Float for T TCK TDO Figure 20. Output Delay and Output Float Waveform for T TCK Non-Test Outputs Figure 21. Input Setup and Hold Waveform for T TCK Non-Test Inputs 50 and T ...

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Figure 22. Rise and Fall Time Derating at 85 °C and Minimum 50pF Figure 23. I Active (Power Supply) vs. Frequency CC 1800 1600 1400 1200 1000 800 600 400 200 Datasheet 100pF C ...

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Figure 24. I Active (Thermal) vs. Frequency CC 1400 1200 1000 800 600 400 200 Figure 25. Output Delay or Hold vs. Load Capacitance CLKIN Frequency (MHz) nom + 10 5.5 V Input Signals nom ...

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Figure 26. Output Delay vs. Temperature Figure 27. Output Hold Times vs. Temperature Figure 28. Output Delay vs. V Datasheet Processor Case Temperature (°C) 0°C nom - 0.0 nom - 0.1 nom - 0.2 nom - 0.3 nom - 0.4 ...

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CLKIN V VCC5, CC, ONCE CT3:0, ADS, LOCK, WAIT, DEN, BLAST W/R, DT/R, BREQ, FAIL, BSTALL A31:2, SUP D/C, BE3:0 D31:0, Inputs DP3:0 STEST RESET CLKIN and V minimum 10,000 CLKIN periods for PLL stabilization. NOTE: V stable: As specified ...

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CLKIN ADS, LOCK, WAIT, DEN, BLAST, W/R, BREQ, FAIL, BSTALL DT/R SUP, A31:2, D/C, BE3:0 D31:0, DP3:0 STEST Maximum Low to RESET 16 CLKIN Periods RESET Valid State RESET Thold Tsetup 1 CLKIN 1 CLKIN RESET High to First Bus ...

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CLKIN V VCC5 CC, ADS, BE3:0, A31:2, D31:0, LOCK, WAIT, BLAST,W/R, D/C, DEN, DT/R, HOLDA, BLAST, FAIL, SUP,BREQ, CT3:0, BSTALL, DP3:0, PCHK ONCE mode is entered within 1 CLKIN period after ONCE becomes low while RESET is low. RESET ONCE ...

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Figure 32. Non-Burst, Non-Pipelined Requests without Wait States PMCON External Function Ready Control Bit 29 Disabled Value NOTE: CLKIN ADS A31:2, SUP, BE3:0, D/C, LOCK, CT3:0 W/R BLAST DT/R DEN WAIT D31:0, DP3:0 PCHK Datasheet Pipe- Bus Parity Odd Burst ...

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Figure 33. Non-Burst, Non-Pipelined Read Request with Wait States PMCON External Ready Function Control Bit Disabled Value NOTE: CLKIN ADS A31:2, BE3:0 W/R BLAST DT/R DEN D/C, SUP, LOCK, CT3:0 WAIT D31:0, DP3:0 PCHK 58 Pipe- Bus Parity Odd ...

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Figure 34. Non-Burst, Non-Pipelined Write Request with Wait States PMCON Function Bit Value CLKIN ADS A31:2, BE3:0 W/R BLAST DT/R DEN D/C, SUP, LOCK, CT3:0 WAIT D31:0, DP3:0 PCHK Datasheet External Pipe- Parity Bus Odd Ready Burst Lining Parity Enable ...

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Figure 35. Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus PMCON External Function Ready Control Bit Disabled Value NOTE: CLKIN ADS A31:4, SUP, CT3:0,D/C, BE3:0, LOCK W/R BLAST DT/R DEN A3:2 WAIT D31:0, DP3:0 PCHK 60 Pipe- Bus ...

Page 61

Figure 36. Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus PMCON External Function Ready Control Bit Disabled Value NOTE: CLKIN ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK W/R BLAST DT/R DEN A3:2 WAIT D31:0, DP3:0 PCHK Datasheet Pipe- Bus ...

Page 62

Figure 37. Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus PMCON External Function Ready Control Bit 29 Disabled Value 0 NOTE: CLKIN ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK W/R BLAST DT/R DEN A3:2 WAIT D31:0, DP3:0 PCHK ...

Page 63

Figure 38. Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus PMCON External Function Ready Control Bit 29 Disabled Value 0 NOTE: CLKIN ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK W/R BLAST DT/R DEN A3:2 WAIT D31:0, DP3:0 PCHK Datasheet ...

Page 64

Figure 39. Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus PMCON External Function Ready Control Bit 29 Disabled Value 0 NOTE: CLKIN ADS SUP, CT3:0, D/C, LOCK, A31:4, BE3/BHE, BE0/BLE W/R BLAST DT/R DEN A3:2 BE1/A1 WAIT D31:0, ...

Page 65

Figure 40. Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus PMCON External Function Ready Control Bit Disabled Value NOTE: CLKIN ADS SUP, CT3:0, D/C, LOCK, A31:4 W/R BLAST DT/R DEN A3:2 BE1/A1, BE0/A0 WAIT D31:0, DP3:0 PCHK Datasheet Pipe- ...

Page 66

Figure 41. Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus PMCON External Function Ready Control Bit 29 X Value x NOTE: CLKIN ADS A31:4, SUP, CT3:0, D/C, LOCK W/R A3:2 BE3:0 D31:0, DP3:0 WAIT BLAST DT/R DEN PCHK ...

Page 67

Figure 42. Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus PMCON External Ready Function Control Bit 29 Disabled X Value x NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. CLKIN ADS A31:4, SUP, CT3:0, D/C, LOCK W/R A3:2 ...

Page 68

Figure 43. Burst, Pipelined Read Request without Wait States, 32-Bit Bus PMCON External Function Ready Control Bit 29 X Value x NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. CLKIN A31:4, SUP, CT3:0, D/C, BE3:0, LOCK D31:0, DP3:0 ...

Page 69

Figure 44. Burst, Pipelined Read Request with Wait States, 32-Bit Bus PMCON External Function Ready Control Bit 29 Enabled X Value x NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. 1 CLKIN ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK ...

Page 70

Figure 45. Burst, Pipelined Read Request with Wait States, 8-Bit Bus PMCON External Function Ready Control Bit 29 X Value x NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. 1 CLKIN ADS A31:4, SUP, CT3:0, D/C, LOCK W/R ...

Page 71

Figure 46. Burst, Pipelined Read Request with Wait States, 16-Bit Bus PMCON External Function Ready Control Bit 29 X Value x NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. CLKIN ADS A31:4, SUP, CT3:0, D/C, BE0/BLC, BE3/BHE, LOCK W/R ...

Page 72

Figure 47. Using External READY CLKIN ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK W/R BLAST DT/R DEN READY BTERM A3:2 WAIT D31:0, DP3:0 PCHK NOTE: Pipelining must be disabled to use READY. 72 Quad-Word Read Request ...

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Figure 48. Terminating a Burst with BTERM CLKIN ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK W/R BLAST DT/R DEN READY BTERM A3:2 WAIT D31:0, DP3:0 PCHK Datasheet Quad-Word Read Request RAD RDD Ready ...

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Figure 49. BREQ and BSTALL Operation CLKIN ADS BLAST BREQ BSTALL The processor may stall (BSTALL asserted) even with an empty bus queue (BREQ deasserted). Depending on the instruction stream and memory wait states, the two signals may be ...

Page 75

Figure 50. BOFF Functional Timing. BOFF occurs during a burst or non-burst data cycle. CLKIN ADS BLAST READY BOFF A31:2, SUP, CT3:0, D/C, BE3:0, WAIT, DEN, DT/R DP3:0 & D31:0, (WRITES) PCHK Note: READY/BTERM must be enabled; N Datasheet BOFF ...

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Figure 51. HOLD Functional Timing CLKIN ADS A31:2, SUP, CT3:0, D/C, BE3:0, WAIT, DEN, DT/R BLAST LOCK HOLD HOLDA 76 Word Read Request Word Read Request N N Hold State N =1, =1 RAD RAD XDA N XDA Valid ...

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Figure 52. LOCK Delays HOLDA Timing CLKIN ADS W/R BLAST LOCK HOLD HOLDA Figure 53. FAIL Functional Timing RESET FAIL 80960HA: 80960HD: 80960HT: Datasheet (Internal Self-Test) Pass Fail 113 Cycles 257,517 Cycles 30 Cycles 15 Cycles 94 Cycles 128,761 Cycles ...

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Figure 54. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions 0 Byte Offset Word Offset 0 Short-Word Load/Store Word Load/Store Double-Word Load/Store NOTES: 1. All requests that are less than a word in size and are cacheable ...

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Figure 55. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions (Continued) 0 Byte Offset 0 Word Offset Triple-Word Load/Store Quad-Word Load/Store NOTES: 1. All requests that are less than a word in size and are cacheable will be ...

Page 80

Figure 56. A Summary of Aligned and Unaligned Transfers for 16-Bit Bus 0 Byte Offset Word Offset 0 Short 16-Bit Bus Word 16-Bit Bus Double Word 16-Bit Bus Triple Word 16-Bit Bus Quad Word 16-Bit Bus ...

Page 81

Figure 57. A Summary of Aligned and Unaligned Transfers for 8-Bit Bus Byte Offset 0 Word Offset 0 Short 8-Bit Bus Word 8-Bit Bus Double Word 8-Bit Bus Triple Word 8-Bit Bus Quad Word 16-Bit Bus Datasheet ...

Page 82

Figure 58. Idle Bus Operation CLKIN ADS A31:4, SUP, D/C, BE3:0, CT3:0 LOCK W/R BLAST DT/R DEN A3:2 WAIT D31:0 READY, BTERM PCHK 82 Write Request Idle Bus N = (not in Hold Acknowledge state) WAD ...

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Figure 59. Bus States Tb BOFF !BOFF !RESET and !HOLD and REQUEST To RESET and !ONCE ONCE and RESET Ti RESET NOTES: 1. When the PMCON for the region has External Ready Control enabled, wait states are inserted as long ...

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Boundary Scan Chain Table 26. 80960Hx Boundary Scan Chain (Sheet DP3 DP2 DP0 DP1 STEST FAILBAR Enable for FAILBAR, BSTALL and BREQ ONCEBAR BOFFBAR Enable ...

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Table 26. 80960Hx Boundary Scan Chain (Sheet D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 BTERMBAR RDYBAR HOLD HOLDA Enable for HOLDA control ADSBAR BE3BAR BE2BAR BE1BAR BE0BAR BLASTBAR DENBAR WRRDBAR DTRBAR Enable ...

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Table 26. 80960Hx Boundary Scan Chain (Sheet LOCKBAR BREQ A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 Enable for A(31:0) and CT(3:0) A15 A14 A13 A12 A11 ...

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Table 26. 80960Hx Boundary Scan Chain (Sheet XINT7BAR XINT6BAR XINT5BAR XINT4BAR XINT3BAR XINT2BAR XINT1BAR XINT0BAR RESETBAR CLKIN CT3 CT2 CT1 CT0 PCHK PCHK enable NOTES: 1. Cell#1 connects to TDO and cell #112 connects to TDI. ...

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... Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet Copyright Intel Corp. 1995 - - *************************************************************************** - - Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein *************************************************************************** - - Boundary-Scan Description Language (BSDL Version 0 ...

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Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet Project code HA -- File **NOT** verified electrically -- ------------------------------------------------ -- Rev 0.7 18 Dec -- Rev 0.6 08 Dec -- Rev 0.5 21 Nov ...

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Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet SUPBAR TCK TDI TDO TMS TRST WAITBAR WRBAR XINTBAR FIVEVREF VCCPLL VOLTDET VCC1 VCC2 VSS1 VSS2 NC ); use STD_1149_1_1990.all; use i960ha_a.all; attribute PIN_MAP of ...

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Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet “D “ “ “ “DENBAR “DP “DTRBAR “DCBAR “FAILBAR “HOLD “HOLDA “LOCKBAR “NMIBAR “ONCEBAR “PCHKBAR “READYBAR “RESETBAR “STEST “SUPBAR “TCK “TDI “TDO “TMS “TRST “WAITBAR “WRBAR ...

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Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet attribute Tap_Scan_In attribute Tap_Scan_Mode attribute Tap_Scan_Out attribute Tap_Scan_Reset of attribute Tap_Scan_Clock of attribute Instruction_Length of Ha_Processor: entity is 4; attribute Instruction_Opcode of Ha_Processor: entity is ...

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Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet attribute Boundary_Cells of Ha_Processor: entity is “BC_4, BC_1, CBSC_1”; attribute Boundary_Length of Ha_Processor: entity is 112; attribute Boundary_Register of Ha_Processor: entity is “0 (CBSC_1, “1 (CBSC_1, ...

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Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet “35 (CBSC_1, “36 (CBSC_1, “37 (CBSC_1, “38 (CBSC_1, “39 (CBSC_1, “40 (CBSC_1, “41 (CBSC_1, “42 (BC_4, “43 (BC_4, “44 (BC_4, “45 (BC_1, “46 (BC_1, “47 ...

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Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet “74 (BC_1, “75 (BC_1, “76 (BC_1, “77 (BC_1, “78 (BC_1, “79 (BC_1, “80 (BC_1, “81 (BC_1, “82 (BC_1, “83 (BC_1, “84 (BC_1, “85 (BC_1, “86 (BC_1, ...

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... Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet Copyright Intel Corporation 1995, 1996 -- ***************************************************************************** -- Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. -- ***************************************************************************** -- Boundary-Scan Description Language (BSDL Version 0 ...

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Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet entity Ha_Processor is generic(PHYSICAL_PIN_MAP : string:= “PQ2”); port (A ADSBAR BEBAR BLASTBAR BOFFBAR BREQ BSTALL BTERMBAR CT CLKIN D DENBAR DP DTRBAR DCBAR FAILBAR HOLD HOLDA ...

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Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet VCC1 VCC2 VSS1 VSS2 ); use STD_1149_1_1990.all; use i960ha_a.all; attribute PIN_MAP of Ha_Processor : entity is PHYSICAL_PIN_MAP; constant PQ2:PIN_MAP_STRING := “A “ “ “ADSBAR “BEBAR ...

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Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet “ONCEBAR “PCHKBAR “READYBAR “RESETBAR “STEST “SUPBAR “TCK “TDI “TDO “TMS “TRST “WAITBAR “WRBAR “XINTBAR “FIVEVREF “VCCPLL “VCC1 “ “VCC2 “ “ “VSS1 “ “VSS2 “ “ ...

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Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet “BYPASS “EXTEST “SAMPLE “IDCODE “RUBIST “CLAMP “HIGHZ “Reserved attribute Instruction_Capture of Ha_Processor: entity is “0001”; attribute Instruction_Private of Ha_Processor: entity is “Reserved” ; attribute Idcode_Register ...

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Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet “6 (BC_1, “7 (BC_4, “8 (BC_4, “9 (CBSC_1, “10 (CBSC_1, “11 (CBSC_1, “12 (CBSC_1, “13 (CBSC_1, “14 (CBSC_1, “15 (CBSC_1, “16 (CBSC_1, “17 (BC_1, “18 (CBSC_1, ...

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Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet “41 (CBSC_1, “42 (BC_4, “43 (BC_4, “44 (BC_4, “45 (BC_1, “46 (BC_1, “47 (BC_1, “48 (BC_1, “49 (BC_1, “50 (BC_1, “51 (BC_1, “52 (BC_1, “53 ...

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Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet “76 (BC_1, “77 (BC_1, “78 (BC_1, “79 (BC_1, “80 (BC_1, “81 (BC_1, “82 (BC_1, “83 (BC_1, “84 (BC_1, “85 (BC_1, “86 (BC_1, “87 (BC_1, “88 (BC_1, ...

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