MPC860SRCVR66D4 Freescale Semiconductor, MPC860SRCVR66D4 Datasheet

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... To locate published errata or updates for this document, refer to the MPC860 product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office. © Freescale Semiconductor, Inc., 2001–2007. All rights reserved. MPC860EC Rev. 8, 08/2007 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 ...

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... MPC855T User’s Manual (MPC855TUM, Rev. 1) MPC860 PowerQUICC™ Family Hardware Specifications, Rev Table 1. MPC860 Family Functionality Ethernet Data Cache 10T 10/100 — — — ATM SCC Reference — Yes 2 1 Yes 2 1 — Yes 4 1 Yes 4 1 Yes 4 1 Yes 1 2 Freescale Semiconductor ...

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... On-chip bus arbitration logic • General-purpose timers — Four 16-bit timers or two 32-bit timers — Gate mode can enable/disable counting — Interrupt can be masked on reference match and event capture. MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Features Table 1) 3 ...

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... Communications processor module (CPM) — RISC communications processor (CP) — Communication-specific commands (for example, , and MODE RESTART TRANSMIT — Supports continuous mode transmission and reception on all serial channels MPC860 PowerQUICC™ Family Hardware Specifications, Rev GRACEFUL STOP TRANSMIT ) , ENTER HUNT Freescale Semiconductor ...

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... Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation — Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined — 8-bit resolution — Allows independent transmit and receive routing, frame synchronization, and clocking MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Features 5 ...

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... Supports conditions: = ≠ < > — Each watchpoint can generate a break-point internally. • 3.3-V operation with 5-V TTL compatibility except EXTAL and EXTCLK • 357-pin ball grid array (BGA) package MPC860 PowerQUICC™ Family Hardware Specifications, Rev Freescale Semiconductor ...

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... MPC860 is unpowered, voltage greater than 2.5 V must not be applied to its inputs). 3 Minimum temperatures are guaranteed as ambient temperature, T temperature MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Table 2. Maximum Tolerated Ratings Symbol KAPWR V . Maximum temperatures are guaranteed as junction A Maximum Tolerated Ratings Table 2 ) ...

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... Figure 1. Undershoot/Overshoot Voltage for V 4 Thermal Characteristics Package Designator ZP ZQ/VR MPC860 PowerQUICC™ Family Hardware Specifications, Rev 20 DDL GND Not to Exceed 10 interface Table 3. Package Description Package Code (Case No.) 5050 (1103-01) 5058 (1103D-02) 1 and V DDH DDL Package Description PBGA 357 25*25*0.9P1.27 PBGA 357 25*25*1.2P1.27 Freescale Semiconductor ...

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... Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Table 4. MPC860 Thermal Resistance Data Environment Single-layer board (1s) Four-layer board (2s2p) ...

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... TBD TBD 722 762 851 909 Min Max 3.0 3.6 2.0 3.6 V – 0.4 V DDH DDH 3.135 3.465 2.0 3.6 V – 0.4 V DDH DDH 2.0 5.5 GND 0.8 0.7 × 0.3 DDH DDH — 100 Freescale Semiconductor Unit Unit µA ...

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... MII_TXD[0:3] 4 BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6)/CE(1)_B, CS(7)/CE(2)_B, WE0/BS_B0/IORD, WE1/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, GPL_A(2:3)/GPL_B(2:3)/ CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A, ALE_B/DSCK/AT1, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, and BADDR(28:30) MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Symbol ...

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... MPC860 PowerQUICC™ Family Hardware Specifications, Rev × PI/O, where PI/O is the power dissipation of the I ºC can be obtained from the equation: J × – are possible θCA . For instance, the user can change the airflow around θCA Figure 2. Freescale Semiconductor ...

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... (Ψ MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Board Temperature Rise Above Ambient Divided by Package Power × can be used to determine the junction temperature with Thermal Calculation and Measurement ...

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... Special care should be taken to minimize the noise levels on the PLL supply pins. MPC860 PowerQUICC™ Family Hardware Specifications, Rev (415) 964-5111 800-854-7179 or 303-397-7956 http://www.jedec.org power supply should be bypassed to ground using at least DD and GND should be kept to less than half DD and GND planes is CC Freescale Semiconductor ...

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... RD/WR, BURST, D(0:31), DP(0:3) valid B8a CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3) BDIP, PTR valid B8b CLKOUT to BR, BG, VFLS(0:1), VF(0:2), IWP(0:2), FRZ, LWP(0:1), STS valid MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Table 7. Bus Operation Timings 33 MHz 40 MHz Min Max Min 30.30 30 ...

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... Freescale Semiconductor Unit Max 10.04 ns 11.29 ns 9.75 ns 8.54 ns 9.00 ns 14.04 ns 15.00 ns 9.00 ns 15.00 ns — ns — ns — ...

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... GPCM write access, ACS = 00, TRLX = 0, 1, and CSNT = 0 B29c CS negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 0, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 0 MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Table 7. Bus Operation Timings (continued) 33 MHz Min Max Min 2.00 8 ...

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... Freescale Semiconductor Unit Max — ns — ns — ns — ns — ns — ns — ns — ns — ns — ns — ns 6.00 ...

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... CST1 in the corresponding word in UPM B34b A(0:31), BADDR(28:30), and D(0:31 valid—as requested by control bit CST2 in the corresponding word in UPM MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Table 7. Bus Operation Timings (continued) 33 MHz Min Max Min 7.58 14 ...

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... TBD — TBD — Figure 18. Freescale Semiconductor Unit Max — ns — ns — ns — ns — ns — ns — ns — ns — ns — ns TBD ns ...

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... Inputs A Maximum output delay specification. B Minimum output hold time. C Minimum input setup time specification. D Minimum input hold time specification. Figure 4 provides the timing for the external clock. CLKOUT MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Figure 3. Control Timing Figure 4. External Clock Timing ...

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... CLKOUT TS, BB TA, BI TEA Figure 6. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing MPC860 PowerQUICC™ Family Hardware Specifications, Rev B8a B9 B8b B11 B12 B11a B12a B14 B15 B13 B13a Freescale Semiconductor ...

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... Figure 8 provides normal case timing for input data. It also applies to normal read accesses under the control of the UPM in the memory controller. CLKOUT TA D[0:31], DP[0:3] MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor B16 B16a B16b B16 B17 B18 B19 Figure 8. Input Data Timing in Normal Case ...

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... GPCM factors. CLKOUT TS A[0:31] CSx OE WE[0:3] D[0:31], DP[0:3] Figure 10. External Bus Read Timing (GPCM Controlled—ACS = 00) MPC860 PowerQUICC™ Family Hardware Specifications, Rev B20 B21 B11 B12 B8 B22 B25 B28 B18 B23 B26 B19 Freescale Semiconductor ...

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... Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor B11 B12 B8 B22a B24 B25 B18 B11 B12 B22b ...

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... Bus Signal Timing CLKOUT B11 TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = ACS = 10, ACS = 11) MPC860 PowerQUICC™ Family Hardware Specifications, Rev B12 B8 B22a B27 B27a B22b B22c B18 B23 B26 B19 Freescale Semiconductor ...

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... GPCM factors. CLKOUT TS A[j0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 0) MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor B11 B12 B8 B22 B25 B26 B8 Bus Signal Timing B30 B23 B28 ...

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... Bus Signal Timing CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 1) MPC860 PowerQUICC™ Family Hardware Specifications, Rev B11 B12 B8 B28b B28d B22 B25 B26 B28a B28c B8 B30a B30c B23 B29c B29g B29a B29f B9 Freescale Semiconductor ...

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... CLKOUT B11 TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 1) MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor B12 B8 B22 B25 B26 B8 Bus Signal Timing B30b B30d B28b B28d B23 B29e B29i B29d B29h ...

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... A[0:31] CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 17. External Bus Timing (UPM Controlled Signals) MPC860 PowerQUICC™ Family Hardware Specifications, Rev B31a B31d B31 B34 B34a B34b B32a B32d B32 B35 B36 B35a B35b B33 B31c B31b B32c B32b B33a Freescale Semiconductor ...

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... UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 19. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor B38 B38 Bus Signal Timing 31 ...

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... Figure 22 provides the timing for the asynchronous external master control signals negation. AS CSx, WE[0:3], OE, GPLx, BS[0:3] Figure 22. Asynchronous External Master—Control Signals Negation Timing MPC860 PowerQUICC™ Family Hardware Specifications, Rev B41 B42 B40 B39 B40 B43 B22 B22 Freescale Semiconductor ...

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... Figure 23. Interrupt Detection Timing for External Level Sensitive Lines Figure 24 provides the interrupt detection timing for the external edge-sensitive lines. CLKOUT IRQx Figure 24. Interrupt Detection Timing for External Edge Sensitive Lines MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Table 8. Interrupt Timing 1 Characteristic I39 I41 I43 ...

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... Freescale Semiconductor Unit ...

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... PCMCIA access cycle timing for the external bus read. CLKOUT TS A[0:31] REG CE1/CE2 PCOE, IORD ALE D[0:31] Figure 25. PCMCIA Access Cycle Timing External Bus Read MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor P44 P46 P45 P48 P50 P52 P53 B18 Bus Signal Timing P47 ...

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... Figure 26. PCMCIA Access Cycle Timing External Bus Write Figure 27 provides the PCMCIA WAIT signal detection timing. CLKOUT WAITx Figure 27. PCMCIA WAIT Signal Detection Timing MPC860 PowerQUICC™ Family Hardware Specifications, Rev P44 P46 P45 P48 P50 P52 P53 B8 P55 P56 P47 P49 P51 P54 P52 B9 Freescale Semiconductor ...

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... CLKOUT Output Signals HRESET OP2, OP3 Figure 29 provides the PCMCIA output port timing for the MPC860. CLKOUT Input Signals MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Table 10. PCMCIA Port Timing 33 MHz 40 MHz Min Max Min — 19.00 — 1 25.73 — ...

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... Figure 30. Debug Port Clock Input Timing D64 D65 D66 D67 Figure 31. Debug Port Timings All Frequencies Min Max 3 × T — CLOCKOUT 1.25 × T — CLOCKOUT 0.00 3.00 8.00 — 5.00 — 0.00 15.00 0.00 2.00 D62 D63 Freescale Semiconductor Unit — — ...

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... HRESET to data out high impedance R80 DSDI, DSCK setup R81 DSDI, DSCK hold time R82 SRESET negated to CLKOUT rising edge for DSDI and DSCK sample MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Table 12. Reset Timing 33 MHz 40 MHz Min Max Min Max — ...

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... CLKOUT HRESET RSTCONF D[0:31] (OUT) (Weak) Figure 33. Reset Timing—Data Bus Weak Drive During Configuration MPC860 PowerQUICC™ Family Hardware Specifications, Rev R71 R76 R73 R74 R75 R69 R79 R77 R78 Freescale Semiconductor ...

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... J94 TCK falling edge to output high impedance J95 Boundary scan input valid to TCK rising edge J96 TCK rising edge to boundary scan input invalid MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor R70 R82 R80 R80 R81 Figure 35 Table 13. JTAG Timing Characteristic IEEE 1149 ...

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... Figure 38. Boundary Scan (JTAG) Timing Diagram MPC860 PowerQUICC™ Family Hardware Specifications, Rev J82 J83 J82 J84 Figure 35. JTAG Test Clock Input Timing J85 J86 J87 J88 J91 J90 Figure 37. JTAG TRST Timing Diagram J92 J93 J83 J84 J89 J94 J95 J96 Freescale Semiconductor ...

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... Data-in hold time from clock high 31 Clock low to data-out valid (CPU writes data, control, or direction Specification 23. DATA-IN STBI STBO Figure 39. PIP Rx (Interlock Mode) Timing Diagram MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Figure 39 Table 14. PIP/PIO Timing Characteristic CPM Electrical Characteristics through Figure 43 ...

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... STBO (Output) STBI (Input) Figure 40. PIP Tx (Interlock Mode) Timing Diagram DATA-IN STBI (Input) STBO (Output) Figure 41. PIP Rx (Pulse Mode) Timing Diagram DATA-OUT STBO (Output) STBI (Input) Figure 42. PIP TX (Pulse Mode) Timing Diagram MPC860 PowerQUICC™ Family Hardware Specifications, Rev Freescale Semiconductor ...

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... Table 16 provides the IDMA controller timings as shown in Num 40 DREQ setup time to clock high 41 DREQ hold time from clock high MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor 29 31 Table 15. Port C Interrupt Timing Characteristic 35 Figure 44. Port C Interrupt Detection Timing Figure 45 Table 16. IDMA Controller Timing ...

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... Figure 45. IDMA External Requests Timing Diagram CLKO (Output) TS (Output) R/W (Output) DATA TA (Input) SDACK Figure 46. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA MPC860 PowerQUICC™ Family Hardware Specifications, Rev Characteristic All Frequencies Min Max — 12 — 12 — 20 — — Freescale Semiconductor Unit ...

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... R/W (Output) DATA TA (Output) SDACK Figure 47. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 48. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor CPM Electrical Characteristics 45 47 ...

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... CLKO low to TOUT valid MPC860 PowerQUICC™ Family Hardware Specifications, Rev Figure Table 17. Baud Rate Generator Timing Characteristic Table 18. Timer Timing Characteristic 49. All Frequencies Min Max — — 51 Figure 50. All Frequencies Min Max 10 — 1 — 2 — 3 — Freescale Semiconductor Unit Unit ns CLK CLK CLK ns ...

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... L1CLK edge to L1TXD valid 80A L1TSYNC valid to L1TXD valid 81 L1CLK edge to L1TXD high impedance 82 L1RCLK, L1TCLK frequency (DSC = L1RCLK, L1TCLK width low (DSC = 1) 83a L1RCLK, L1TCLK width high (DSC = 1) MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Figure 51 Table 19. SI Timing Characteristic ...

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... Figure 51. SI Receive Timing Diagram with Normal Clocking (DSC = 0) MPC860 PowerQUICC™ Family Hardware Specifications, Rev Table 19. SI Timing (continued) Characteristic 4 70 71a 72 RFSD BIT0 76 78 All Frequencies Unit Min Max — 30.00 ns 1.00 — L1TCL K 42.00 — ns 42.00 — ns — 0. Freescale Semiconductor ...

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... L1RCLK ( (Input) 82 L1RCLK ( (Input) L1RSYNC (Input) 73 L1RXD (Input) 76 L1ST(4–1) (Output) L1CLKO (Output) Figure 52. SI Receive Timing with Double-Speed Clocking (DSC = 1) MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor 72 83a RFSD BIT0 78 84 CPM Electrical Characteristics 79 51 ...

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... CPM Electrical Characteristics L1TCLK ( (Input) 71 L1TCLK ( (Input) 73 L1TSYNC (Input) L1TXD (Output) L1ST(4–1) (Output) Figure 53. SI Transmit Timing Diagram (DSC = 0) MPC860 PowerQUICC™ Family Hardware Specifications, Rev TFSD 80a BIT0 Freescale Semiconductor ...

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... L1RCLK ( (Input) L1RCLK ( (Input) L1RSYNC (Input) 73 L1TXD BIT0 (Output) 80 L1ST(4–1) (Output) 84 L1CLKO (Output) Figure 54. SI Transmit Timing with Double Speed Clocking (DSC = 1) MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor 72 83a 82 TFSD 78a 78 CPM Electrical Characteristics 79 53 ...

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... CPM Electrical Characteristics MPC860 PowerQUICC™ Family Hardware Specifications, Rev Figure 55. IDL Timing Freescale Semiconductor ...

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... The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 3/1. 2 Also applies to CD and CTS hold time when they are used as external sync signals. MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Table 20. NMSI External Clock Timing Characteristic 1 2 Table 21. NMSI Internal Clock Timing ...

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... Figure 56. SCC NMSI Receive Timing Diagram TCLK1 102 TxD1 (Output) RTS1 (Output) CTS1 (Input) CTS1 (SYNC Input) Figure 57. SCC NMSI Transmit Timing Diagram MPC860 PowerQUICC™ Family Hardware Specifications, Rev 102 101 100 107 102 101 100 103 105 104 108 107 104 107 Freescale Semiconductor ...

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... TXD1 active delay (from TCLK1 rising edge) 132 TXD1 inactive delay (from TCLK1 rising edge) 133 TENA active delay (from TCLK1 rising edge) 134 TENA inactive delay (from TCLK1 rising edge) MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor 102 101 100 103 104 107 105 Figure 58 ...

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... Figure 60. Ethernet Receive Timing Diagram MPC860 PowerQUICC™ Family Hardware Specifications, Rev Table 22. Ethernet Timing (continued) Characteristic 2 2 120 121 124 125 All Frequencies Min Max — — 20 — 20 121 123 Last Bit 126 127 Freescale Semiconductor Unit ns ns CLK ns ns ...

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... RxD1 0 (Input) Start Frame Delimiter RSTRT (Output) Figure 62. CAM Interface Receive Start Timing Diagram REJECT Figure 63. CAM Interface REJECT Timing Diagram MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor 128 121 132 1 1 BIT1 125 137 CPM Electrical Characteristics 129 ...

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... Figure 64. SMC Transparent Timing Diagram MPC860 PowerQUICC™ Family Hardware Specifications, Rev Figure Table 23. SMC Transparent Timing Characteristic 151A 152 151 150 Note 1 154 155 154 155 64. All Frequencies Min Max 100 — 50 — 50 — — — 5 — 153 Freescale Semiconductor Unit ...

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... SPICLK ( (Output) 163 SPIMISO msb (Input) 167 SPIMOSI msb (Output) Figure 65. SPI Master ( Timing Diagram MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Figure 65 Table 24. SPI Master Timing Characteristic 167 166 160 167 162 166 Data lsb 165 164 ...

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... Data 165 msb Data Figure 67 Table 25. SPI Slave Timing Characteristic lsb 164 166 lsb and Figure 68. All Frequencies Min Max 2 — 15 — 15 — 1 — 1 — 20 — 20 — — 50 Freescale Semiconductor msb msb Unit t cyc cyc t cyc ...

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... SPICLK ( (Input) 177 SPIMISO Undef (Output) 175 SPIMOSI (Input) Figure 68. SPI Slave ( Timing Diagram MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor 172 182 181 170 181 182 180 Data lsb 179 181 182 Data lsb 172 ...

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... Freescale Semiconductor Unit kHz kHz μs μs μs μs μs μs ns μs ns μs Unit ...

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... UTPB, SOC, Rxclav and Txclav setup time U4 UTPB, SOC, Rxclav and Txclav hold time U5 UTPB, SOC active delay (and PHREQ and PHSEL active delay in MPHY mode) MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor 203 204 207 209 210 2 Figure 69. I ...

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... UTOPIA receive operations. UtpClk U5 PHREQ n RxClav RxEnb UTPB SOC Figure 71 shows signal timings during UTOPIA transmit operations. UtpClk U5 5 PHSEL n TxClav TxEnb UTPB SOC MPC860 PowerQUICC™ Family Hardware Specifications, Rev Figure 70. UTOPIA Receive Timing Figure 71. UTOPIA Transmit Timing Freescale Semiconductor ...

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... MII_RX_CLK pulse width low Figure 72 shows MII receive signal timing. MII_RX_CLK (Input) MII_RXD[3:0] (Inputs) MII_RX_DV MII_RX_ER Figure 72. MII Receive Signal Timing Diagram MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Table 29. MII Receive Signal Timing Characteristic FEC Electrical Characteristics Min Max ...

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... MII transmit signal timing diagram. MII_TX_CLK (Input) RMII_REFCLK MII_TXD[3:0] (Outputs) MII_TX_EN MII_TX_ER Figure 73. MII Transmit Signal Timing Diagram MPC860 PowerQUICC™ Family Hardware Specifications, Rev Table 30. MII Transmit Signal Timing Characteristic Min Max Unit 5 — ns — 65% MII_TX_CLK period 35% 65% MII_TX_CLK period M8 Freescale Semiconductor ...

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... MII_MDIO (input) to MII_MDC rising edge setup M13 MII_MDIO (input) to MII_MDC rising edge hold M14 MII_MDC pulse width high M15 MII_MDC pulse width low MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Table 31. MII Async Inputs Signal Timing Characteristic M9 Characteristic FEC Electrical Characteristics Min Max Unit 1 ...

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... MPC860 PowerQUICC™ Family Hardware Specifications, Rev M14 M10 M11 M12 M13 2 Number of Ethernet Support Multichannel 1 SCCs (Mbps) HDLC Support 1 10/100 2 10 10/100 10/100 10/100 10/100 MM15 ATM Support Yes Yes N/A N/A Yes Yes Yes Yes N/A N/A Yes Yes Yes Yes Yes Yes Freescale Semiconductor ...

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... MPC860. Table 34. MPC860 Family Package/Frequency Availability Package Type Ball grid array ZP suffix—leaded ZQ suffix—leaded VR suffix—lead-free are available as needed MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Mechanical Data and Ordering Information Freq. (MHz) / Package Temp. (Tj ZP/ZQ MPC855TZQ50D4 0° ...

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... KMPC860DEZQ80D4 KMPC860DTZQ80D4 KMPC860ENZQ80D4 KMPC860SRZQ80D4 KMPC860TZQ80D4 KMPC860DPZQ80D4 KMPC860PZQ80D4 1 50 ZP/ZQ MPC855TCZQ50D4 –40° to 95°C MPC860DECZQ50D4 MPC860DTCZQ50D4 MPC860ENCZQ50D4 MPC860SRCZQ50D4 MPC860TCZQ50D4 MPC860DPCZQ50D4 MPC860PCZQ50D4 Tape and Reel MPC855TCZQ50D4R2 1 66 ZP/ZQ MPC855TCZQ66D4 –40° to 95°C MPC860ENCZQ66D4 MPC860SRCZQ66D4 MPC860TCZQ66D4 MPC860DPCZQ66D4 MPC860PCZQ66D4 Order Number Freescale Semiconductor ...

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... PC14 PA14 PC15 A8 PB30 PA15 PB31 A10 A11 MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor NOTE: This is the top view of the device VDDL IRQ0 D13 D27 D10 D14 D18 D20 IRQ1 D8 D23 D11 D16 D19 D21 VDDH D12 D17 ...

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... MPC860 PowerQUICC™ Family Hardware Specifications, Rev 0 18X 357X NOTE C 0.2 C 0. SIDE VIEW MILLIMETERS DIM MIN MAX --- 2.05 A 0.50 0.70 A1 0.95 1.35 A2 0.70 0.90 A3 0.60 0.90 b 25.00 BSC D 22.86 BSC D1 22.40 22.60 D2 1.27 BSC e 25.00 BSC E 22.86 BSC E1 22.40 22.60 E2 Freescale Semiconductor ...

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... Maximum Solder Ball Diameter measured parallel to Datum A. 4. Datum A, the seating plane, is defined by the spherical crowns of the solder balls. Figure 78. Mechanical Dimensions and Bottom Surface Nomenclature of the ZQ PBGA Package MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Mechanical Data and Ordering Information NOTE 75 ...

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... Figure 3, changed all reference voltage measurement points from 0.2 and 0 Table 16, changed num 46 description to read, “TA assertion to rising edge ...” Figure 46, changed TA to reflect the rising edge of the clock. Table 7 -36. by the ZQ package Table 34 Figure 78 Freescale Semiconductor ...

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... THIS PAGE INTENTIONALLY LEFT BLANK MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Document Revision History 77 ...

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... Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC860 PowerQUICC™ Family Hardware Specifications, Rev Freescale Semiconductor ...

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... THIS PAGE INTENTIONALLY LEFT BLANK MPC860 PowerQUICC™ Family Hardware Specifications, Rev. 8 Freescale Semiconductor Document Revision History 79 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...