GCIXP1240AB Intel, GCIXP1240AB Datasheet

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GCIXP1240AB

Manufacturer Part Number
GCIXP1240AB
Description
IC MPU NETWORK 200MHZ 432-BGA
Manufacturer
Intel
Datasheets

Specifications of GCIXP1240AB

Rohs Status
RoHS non-compliant
Processor Type
Network
Features
32-bit StrongARM RISC Core
Speed
200MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
432-BGA
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Other names
837151

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
GCIXP1240AB
Manufacturer:
Intel
Quantity:
10 000
Intel
Specification Update
March 2004
Notice: The IXP1240 may contain design defects or errors known as errata. Characterized errata that
may cause the IXP1240’s behavior to deviate from published specifications are documented in this
specification update.
®
IXP1240 Network Processor
Part Number:
278505-005

Related parts for GCIXP1240AB

GCIXP1240AB Summary of contents

Page 1

... Intel IXP1240 Network Processor Specification Update March 2004 Notice: The IXP1240 may contain design defects or errors known as errata. Characterized errata that may cause the IXP1240’s behavior to deviate from published specifications are documented in this specification update. Part Number: 278505-005 ...

Page 2

... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ...

Page 3

... Contents Preface ...............................................................................................................................................5 Summary Table of Changes...............................................................................................................7 Identification Information................................................................................................................10 Errata................................................................................................................................................11 Specification Changes......................................................................................................................20 Specification Clarifications..............................................................................................................22 Documentation Changes ..................................................................................................................24 Specification Update ® IXP1240 Network Processor Intel iii ...

Page 4

... IXP1240 Network Processor Intel iv Specification Update ...

Page 5

... This document may also contain information that was not previously published. Related Documents IXP1240 Network Processor Datasheet IXP1200 Network Processor Family Hardware Reference Manual Specification Update ® Intel IXP1240 Network Processor Title Preface Part Number 278405 278303 ...

Page 6

... Intel IXP1240 Network Processor Preface Nomenclature Errata are design defects or errors. These may cause the published (component, board, system) behavior to deviate from published specifications. Hardware and software designed to be used with any component, board, and system must consider all errata documented. ...

Page 7

... Summary Table of Changes The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the IXP1250 Network Processor product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. This table uses the following ...

Page 8

... Intel IXP1240 Network Processor Summary Table of Changes Errata No Steppings Page Status B0 – – NoFix X 11 NoFix X 11 NoFix X 12 NoFix X 12 NoFix X 12 NoFix X 12 NoFix X 13 NoFix X 14 NoFix 16 Fixed X 16 NoFix 16 Fixed 16 Fixed 16 Fixed 17 Fixed X 17 NoFix 17 Fixed ...

Page 9

... FCLK AC Parameter Measurements 20 SRAM SCLK Signal AC Parameters 21 SDRAM SDCLK AC Parameters Page SPECIFICATION CLARIFICATIONS – – 22 SRAM Unlocks and Write Unlocks 22 Maximum Number of Chain_Ref Instructions 22 DMA Receive in Big Endian Mode DOCUMENTATION CHANGES None for this release ® Intel IXP1240 Network Processor Summary Table of Changes 9 ...

Page 10

... Intel IXP1240 Network Processor Identification Information Identification Information Markings Product Name GCIXP1240AC GCIXP1240AC GCIXP1240AA GCIXP1240AB GCIXP1240AC 1. Samples only. Figure 1. Package Marking Pin 1 10 Stepping QDF Number 1 A0 Q254 1 B0 Q253 GCIXP1240xx FFFFFFFF INTEL M C 2001 xxxxxxxSz YWW PHILLIPPINES Marketing Version ...

Page 11

... For example, the address of a Descriptor Pointer located at SDRAM address 0x1000 should be right-shifted 1 bit with the resulting operand value being 0x0800, as follows: ; fix address of SDRAM Descriptor Pointer immed[tmp1, 0x1000] alu[DESC_ADDR,--,B,tmp1,>>1] ; issue DMA request pci_dma[DESC_ADDR, 0, any_queue] NoFix Status: Specification Update ® Intel IXP1240 Network Processor Errata 11 ...

Page 12

... Intel IXP1240 Network Processor Errata 4. Clock Setup Time Because the SRAM and SDRAM setup times are directly related to the loading of SCLK and Problem: SDCLK, excessive setup times (T value of T for both memory interfaces is 7.5 ns. su Inability to meet the data setup time specification for memory devices. ...

Page 13

... Without this directive, the compiler may reorder the instructions. 3. Rebuild the VxWorks image. Refer to the README file entitled Building the VxWorks BSP, for directions on how to build the image. NoFix Status: Specification Update ® Intel IXP1240 Network Processor Errata 13 ...

Page 14

... Intel IXP1240 Network Processor Errata 9. SRAM[WRITE_UNLOCK,..., BURST_COUNT] Instruction The SRAM[WRITE_UNLOCK,..., ref_cnt] optional_token(s) instruction does not work correctly Problem: when ref_cnt > 1. Note that the command works correctly when the ref_cnt is equal to 1. The SRAM[WRITE_UNLOCK,…,ref_cnt] command may not be completed by the SRAM unit Implication: when the ref_cnt is greater than 1 ...

Page 15

... SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 3], ctx_swap, defer[1] alu[$x3, --, b, r3] Workaround 1 alu[$x1, --, b, r1] alu[$x2, --, b, r2] alu[$x3, --, b, r3] SRAM[WRITE, $x2, sAddr SRAM[WRITE_UNLOCK, $x1, sAddr, 0, 1], ctx_swap Workaround 2 alu[$x1, --, b, r1] alu[$x2, --, b, r2] alu[$x3, --, b, r3] SRAM[WRITE, $x1, sAddr, 0, 3], sig_done SRAM[UNLOCK, --, sAddr Ctx_arb[SRAM] NoFix Status: Specification Update ® Intel IXP1240 Network Processor Errata 15 ...

Page 16

... Intel IXP1240 Network Processor Errata 10. PCI_OUT_INT_MASK Register Bits Not Readable PCI Out Interrupt Mask register at 34h. The register is write only and cannot be read back. Problem: The mask is operational, but the only way to test generating I Implication: PCI, writing 1 to this register, and then checking if subsequent interrupts to PCI are masked. ...

Page 17

... The Parity bit in the PCI interface is not set correctly. The Parity error indication bit in the PCI_STATUS register is correct. Bad parity. Implication: Use the register parity error indication in the PCI_STATUS register. Workaround: Fixed Status: Specification Update ® Intel IXP1240 Network Processor Errata 17 ...

Page 18

... Intel IXP1240 Network Processor Errata 18. Find Bit Find Bit works on the software model but not in the actual hardware. The operation returns zero Problem: when a non-zero result is expected. ; Demonstration of find_bset_with_mask erratum ; ; The data register is loaded with all 1’s ; Then find_bset_with_mask with a mask of 0x10, ...

Page 19

... When this bit is read, the IXP1240 incorrectly indicates that it is not capable of operating at 66 Implication: MHz as defined in the PCI Local Bus Specification, Revision 2.2. Do not use this bit for determining the maximum operating frequency of the IXP1240’s PCI bus. Workaround: Status: NoFix. Specification Update ® Intel IXP1240 Network Processor Errata 19 ...

Page 20

... Intel IXP1240 Network Processor Specification Changes Specification Changes 1. SRAM Bus Signal Timing Parameters The maximum clock to data output valid delay (T specified as 4.0 ns. The new T The maximum clock to control outputs valid delay (T originally specified as 4.0 ns. The new T The minimum data input setup time before SCLK for pipelined SRAMs (T operation was originally specified as 3 ...

Page 21

... The minimum Cycle Low Time (T The new T value 4.02 ns. low Specification Update Intel ) for 232 MHz operation was originally specified as 8.6 ns. The cyc ) for 232 MHz operation was originally specified as 4.6 ns. high ) for 232 MHz operation was originally specified as 4.6 ns. ...

Page 22

... Intel IXP1240 Network Processor Specification Clarifications Specification Clarifications 1. SRAM Unlocks and Write Unlocks Documentation had indicated that performing an SRAM write_unlock on a memory location that Issue: was not locked would only result in an SRAM write, and that an SRAM unlock on a memory address that was not locked would result in no action ...

Page 23

... Figure 2. Results for DMA Receive in Big Endian Mode - Unaligned Transfer Specification Update ® Intel IXP1240 Network Processor Specification Clarifications 23 ...

Page 24

... Intel IXP1240 Network Processor Documentation Changes Documentation Changes None for this version of the specification update. 24 Specification Update ...

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