EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet

IC EZ80 ACCLAIM 50MHZ 100LQFP

EZ80190AZ050SC00TR

Manufacturer Part Number
EZ80190AZ050SC00TR
Description
IC EZ80 ACCLAIM 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet

Specifications of EZ80190AZ050SC00TR

Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80190AZ050SC00TR
Manufacturer:
Zilog
Quantity:
10 000
eZ80190
Product Specification
PS006614-1208
®
Copyright ©2008 by Zilog
, Inc. All rights reserved.
www.zilog.com

Related parts for EZ80190AZ050SC00TR

EZ80190AZ050SC00TR Summary of contents

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... Product Specification PS006614-1208 ® Copyright ©2008 by Zilog , Inc. All rights reserved. www.zilog.com ...

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... TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. eZ80 and Z80 are registered trademarks of Zilog Inc. All other product or service names are the property of their respective owners. PS006614-1208 ...

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Revision History Each instance in Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appropriate links in the table below. Revision Date Level December 14 2008 March 2006 ...

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Table of Contents Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Chip Select x Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 RAM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 RAM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 RAM Address Upper Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Universal Zilog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Baud Rate Generator Functional Description . . . . . . . . . . . . . . . . . . . . . . . 63 Recommended Usage of the Baud Rate Generator . . . . . . . . . . . . . . . . . . 63 UZI and BRG Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 UZI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 BRG Divisor Latch Registers— ...

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UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 ...

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... DMA Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 DMA Source Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 DMA Destination Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 DMA Byte Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 DMA Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Zilog Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 ZDI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 ZDI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 ZDI Clock and Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 ZDI Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 ZDI Single-Bit Byte Separator ...

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Operation Of The eZ80190 Device During ZDI Breakpoints . . . . . . . . . . . . . . 153 ZDI Write Only Registers . . . . . . . . . . . . . ...

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Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Architectural Overview General Description Zilog’s eZ80190 microprocessor is a high-speed single-cycle instruction-fetch micropro- cessor with a clock speed MHz the first of a new set of products based upon Zilog’s eZ80 The eZ80 CPU is one of the fastest 8-bit CPUs available today, executing code up to four times faster with zero wait-state memory than a standard Z80 quency ...

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... Standard Temperature Range: 0 ºC to +70 ºC – Extended Temperature Range: –40 ºC to +105 ºC • Zilog Debug Interface (ZDI) Note: All signals with an overline are active Low. For example, B/W, for which WORD is active Low, and B/W, for which BYTE is active Low. ...

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... UZI Universal Zilog Interface ( SCL0/1 Serial Interface SDA0/1 (2) SCK0/1 SPI Serial SS0/1 Peripheral Interface MISO0/1 (2) MOSI0/1 CTS0/1 DCD0/1 DSR0/1 UART Universal DTR0/1 Asynchronous Receiver/ RI0/1 Transmitter (2) RTS0/1 RXD0/1 TXD0/1 PS006614-1208 1K Byte MACC Dual-Port Multiply MACC Accumulator SRAM Bus Controller 8K Byte General ...

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Pin Description Figure 2 displays the pin layout of the eZ80190 device in the 100-pin LQFP package. Table 1 on page 5 lists the pins and their functions. MREQ CS0 CS1 CS2 CS3 V DD GND A0 ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device Pin No. Symbol Function 1 MREQ Memory Request 2 WR Write 3 RD Read 4 CS0 Chip Select 0 5 CS1 Chip Select 1 6 CS2 Chip Select 2 7 ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued) Pin No. Symbol Function 10 ADDR0 Address Bus 11 ADDR1 Address Bus 12 ADDR2 Address Bus 13 ADDR3 Address Bus 14 ADDR4 Address Bus 15 ADDR5 Address Bus PS006614-1208 ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued) Pin No. Symbol Function 16 ADDR6 Address Bus 17 ADDR7 Address Bus 18 V Power Supply DD 19 GND Ground 20 ADDR8 Address Bus 21 ADDR9 Address Bus 22 ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued) Pin No. Symbol Function 23 ADDR11 Address Bus 24 ADDR12 Address Bus 25 ADDR13 Address Bus 26 ADDR14 Address Bus 27 ADDR15 Address Bus 28 V Power Supply DD ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued) Pin No. Symbol Function 30 ADDR16 Address Bus 31 ADDR17 Address Bus 32 ADDR18 Address Bus 33 ADDR19 Address Bus 34 ADDR20 Address Bus PS006614-1208 Signal Direction Description Input/Output ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued) Pin No. Symbol Function 35 ADDR21 Address Bus 36 ADDR22 Address Bus 37 ADDR23 Address Bus 38 V Power Supply DD 39 GND Ground 40 DATA0 Data Bus 41 ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued) Pin No. Symbol Function 42 DATA2 Data Bus 43 DATA3 Data Bus 44 DATA4 Data Bus 45 DATA5 Data Bus 46 DATA6 Data Bus 47 DATA7 Data Bus 48 ...

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... Zilog Debug Interface and the eZ80190 device. This pin features an internal pull-up. Input/Output, The ZDA pin is used to transfer data between the Open-Drain with Zilog Debug Interface and the eZ80190 device. Pull-up This pin is open-drain and features an internal pull-up. Input/Output The PB0 pin can be used for GPIO. It can be ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued) Pin No. Symbol Function 58 PB1 GPIO Port B 59 PB2 GPIO Port B 60 PB3 GPIO Port B 61 PB4 GPIO Port B 62 PB5 GPIO Port B ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued) Pin No. Symbol Function 64 PB7 GPIO Port Power Supply DD 66 GND Ground 67 PC0 GPIO Port C MISO1 Master In Slave Out 2 SCL1 ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued) Pin No. Symbol Function 68 PC1 GPIO Port C MOSI1 Master Out Slave In RxD1 Receive Data 2 SDA1 I C Serial Data Input/Output 69 PC2 GPIO Port C ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued) Pin No. Symbol Function 70 PC3 GPIO Port C SS1 Slave Select CTS1 Clear to Send 71 PC4 GPIO Port C DTR1 Data Terminal Ready 72 PC5 GPIO Port ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued) Pin No. Symbol Function 74 PC7 GPIO Port C RI1 Ring Indicator Input, Active Low 75 TEST Test 76 PD0 GPIO Port D MISO0 Master In Slave Out 2 ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued) Pin No. Symbol Function 77 PD1 GPIO Port D MOSI0 Master Out Slave In RxD0 Receive Data 2 SDA0 I C Serial Data Input/Output 78 PD2 GPIO Port D ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued) Pin No. Symbol Function 79 PD3 GPIO Port D SS0 Slave Select CTS0 Clear to Send 80 PD4 GPIO Port D DTR0 Data Terminal Ready 81 PD5 GPIO Port ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued) Pin No. Symbol Function 82 PD6 GPIO Port D DCD0 Data Carrier Detect 83 PD7 GPIO Port D RI0 Ring Indicator Input, Active Low 84 V Power Supply DD ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued) Pin No. Symbol Function 89 PA0 GPIO Port A 90 PA1 GPIO Port A 91 PA2 GPIO Port A 92 PA3 GPIO Port A 93 PA4 GPIO Port A ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued) Pin No. Symbol Function 95 PA6 GPIO Port A 96 PA7 GPIO Port Power Supply DD 98 GND Ground 99 BUSREQ Bus Request 100 PHI System ...

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Register Map All on-chip peripheral registers are accessed in the I/O address space. All I/O operations employ 16-bit addresses. The upper byte of the 24-bit address bus is forced to (ADDR[23:16] = within the range of value from to 00h ...

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Table 2. Register Map (Continued) Address (hex) Mnemonic 8A TMR3_DR_L TMR3_RR_L 8B TMR3_DR_H TMR3_RR_H 8C TMR4_CTL 8D TMR4_DR_L TMR4_RR_L 8E TMR4_DR_H TMR4_RR_H 8F TMR5_CTL 90 TMR5_DR_L TMR5_RR_L 91 TMR5_DR_H TMR5_RR_H 92 Not Accessible Watchdog Timer 93 WDT_CTL 94 WDT_RR 95 ...

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Table 2. Register Map (Continued) Address (hex) Mnemonic 9D PB_ALT2 9E PC_DR 9F PC_DDR A0 PC_ALT1 A1 PC_ALT2 A2 PD_DR A3 PD_DDR A4 PD_ALT1 A5 PD_ALT2 A6 Not Accessible A7 Not Accessible Chip Select/Wait State Generator A8 CS0_LBR A9 CS0_UBR ...

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... Table 2. Register Map (Continued) Address (hex) Mnemonic Universal Zilog Interface Blocks B6 SPI0_CTL B7 SPI0_SR B8 SPI0_RBR B8 SPI0_TSR B9 Not Accessible BA SPI1_CTL BB SPI1_SR BC SPI1_RBR BC SPI1_TSR BD Not Accessible BE Not Accessible BF Not Accessible C0 UART0_RBR UART0_THR BRG0_DLR_L C1 BRG0_DLR_H UART0_IER C2 UART0_IIR UART0_FCTL C3 UART0_LCTL C4 UART0_MCTL C5 UART0_LSR C6 UART0_MSR C7 UART0_SPR C8 I2C0_SAR C9 I2C0_xSAR ...

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Table 2. Register Map (Continued) Address (hex) Mnemonic CA I2C0_DR CB I2C0_CTL CC I2C0_SR I2C0_CCR CD I2C0_SRR CE Not Accessible CF UZI0_CTL D0 UART1_RBR UART1_THR BRG1_DLR_L D1 BRG1_DLR_H UART1_IER D2 UART1_IIR UART1_FCTL D3 UART1_LCTL D4 UART1_MCTL D5 UART1_LSR D6 UART1_MSR ...

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Table 2. Register Map (Continued) Address (hex) Mnemonic DF UZI1_CTL Multiply-Accumulator E0 MACC_xSTART E1 MACC_xEND E2 MACC_xRELOAD E3 MACC_LENGTH E4 MACC_ySTART E5 MACC_yEND E6 MACC_yRELOAD E7 MACC_CTL E8 MACC_AC0 E9 MACC_AC1 EA MACC_AC2 EB MACC_AC3 EC MACC_AC4 ED MACC_STAT DMA ...

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Table 2. Register Map (Continued) Address (hex) Mnemonic F3 DMA0_DAR_U F4 DMA0_BC_L F5 DMA0_BC_H F6 DMA0_CTL F7 DMA1_SAR_L F8 DMA1_SAR_H F9 DMA1_SAR_U FA DMA1_DAR_L FB DMA1_DAR_H FC DMA1_DAR_U FD DMA1_BC_L FE DMA1_BC_H FF DMA1_CTL Notes: 1. After an external pin ...

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... Dual Stack Pointers for ADL (24-bit) and Z80 (16-bit) memory modes • 24-bit CPU registers and ALU • Zilog Debug Interface (ZDI) support • Nonmaskable Interrupt (NMI) + support for 128 vectored interrupts For more information on eZ80 CPU, its instruction set, and eZ80 programming, refer to ® ...

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Programmable Reload Timers Programmable Reload Timers Overview The eZ80190 device features six Programmable Reload Timers (PRT). Each PRT contains a 16-bit downcounter and a 16-bit reload register. In addition, each PRT features a 4-bit clock prescaler with four selectable taps ...

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Programmable Reload Timer Operation Setting Timer Duration There are three factors to consider when determining Programmable Reload Timer dura- tion—clock frequency, clock divider ratio, and initial count value. Minimum duration of the timer is achieved by loading edge. Maximum duration ...

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Table 3. PRT Single-Pass Mode Operation Example Parameter PRT Enabled Reload and Restart Enabled PRT Clock Divider = 2 Single-Pass Mode PRT Interrupt Enabled PRT Reload Value CONTINUOUS Mode In CONTINUOUS mode, when the end-of-count value, matically reloads the 16-bit ...

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Table 4. PRT Continuous Mode Operation Example Parameter PRT Enabled Reload and Restart Enabled PRT Clock Divider = 2 Continuous Mode PRT Interrupt Enabled PRT Reload Value Reading the Current Count Value ® The eZ80 CPU is capable of reading ...

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The Timer Control register can be read or written to. The timer reload registers are Write Only and are located at the same I/O address as the timer data registers, which are Read Only. Timer Control Registers The Timer Control ...

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RST_EN PRT_EN 1 Timer Data Low Byte Register This Read Only register returns the Low byte of the current count value of the selected timer. The Timer Data Low Byte register, listed in in operation. ...

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Data High Byte register. The Timer Data High Byte register value is latched when a read of the Timer Data Low Byte register occurs. Note: The timer data registers and timer reload registers share the same address space. Table 7. ...

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Bit Position Value [7:0] 00h–FFh These bits represent the Low byte of the 2-byte timer TMR_RR_L Timer Reload High Byte Registers The Timer Reload High Byte registers, listed in timer reload value. In CONTINUOUS mode, the timer reload value is ...

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Watchdog Timer WDT Overview The key features of eZ80190 device includes: • Four programmable time-out periods: 2 • A WDT time-out RESET indicator flag • A selectable time-out response: a time-out generates a RESET or a nonmaskable interrupt Figure 6 ...

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WDT Operation Enabling And Disabling The WDT The WDT is disabled upon a system RESET. To enable the WDT, the application program must set the WDT_EN bit (bit 7) of the WDT_CTL register. When enabled, the WDT can- not be ...

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Table 10. WDT Control Register Bit Reset CPU Access Note Read Only; R/W = Read/Write. Bit Position Value Description 7 0 WDT_EN NMI_OUT RST_FLAG 1 [4:2] 000 [1:0] 00 WDT_PERIOD 01 10 ...

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Bit Position Value Description [7:0] A5h WDT_RR 5Ah PS006614-1208 The first write value required to reset the WDT prior to a time- out. The second write value required to reset the WDT prior to a time-out A5h, 5Ah ...

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General-Purpose Input/Output GPIO Overview The eZ80190 device features 32 General-Purpose Input/Output (GPIO) pins. The GPIO pins are assembled as four 8-bit ports—Port A, Port B, Port C, and Port D. All port signals can be configured for use as either ...

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Table 12. GPIO Mode Selection (Continued) GPIO Px_ALT2 Px_ALT1 Px_DDR Mode Bits7:0 Bits7:0 Bits7 ...

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The bit enables a dual-edge-triggered interrupt mode. Both a rising and a GPIO Mode 6— falling edge on the pin cause an interrupt request to be sent to the CPU. Writing the Port x Data register bit ...

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System Clock Mode 1 GPIO Data Mode 4 Register (Output) DATA D Q Bus System Clock Mode 1 Mode 3 GPIO Interrupts Each port pin can be used as an interrupt source. Interrupts can be either level- or edge- triggered. ...

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High. The CPU must be enabled to respond to interrupts for the interrupt request signal to be acted upon. Edge-Triggered Interrupts When the port is configured for edge-triggered interrupts, the corresponding port pin is tristated. If the ...

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Table 13. Port x Data Registers (PA_DR = 96h, PB_DR = 9Ah, PC_DR = 9Eh, PD_DR = A2h) Bit Reset CPU Access Note Undefined; R/W = Read/Write. Port Data Direction Registers x In conjunction with the other GPIO ...

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Table 16. Port x Alternate Registers 2 Bit Reset CPU Access Note: R/W = Read/Write. PS006614-1208 (PA_ALT2 = 99h, PB_ALT2 = 9Dh, PC_ALT2 = A1h, PD_ALT2 = A5h R/W R/W R/W R/W ...

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Chip Selects and Wait States The eZ80190 device generates four Chip Selects for external devices. Each Chip Select may be programmed to access either memory space or I/O space. The Memory Chip Selects can be individually programmed ...

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Depending upon the instruction, either are activated (driven Low) If the upper and lower bounds are set to the same value, such that CSx_UBR = CSx_LBR, then a particular Chip Select is valid for, at most, ...

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CS3_UBR = FFh CS3_LBR = D0h CS2_UBR = CFh CS2_LBR = A0h CS1_LBR = 9Fh CS0_UBR = 7Fh CS0_LBR = CS1_LBR = 00h Figure 8. Memory Chip Select Example Table 17. Register Values for Memory Chip Select Example Chip CSx_CTL[3] ...

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Table 17. Register Values for Memory Chip Select Example (Continued) Chip CSx_CTL[3] CSx_CTL[4] Select CSx_EN CSx_IO CS2 1 0 CS3 1 0 I/O Chip Select Operation I/O Chip Selects can only be active when the CPU is performing I/O instructions. ...

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Depending upon the instruction, either are activated (driven Low) I/O Chip Select Precaution For all I/O operations, the upper byte of the address bus, ADDR[23:16], is forced to The I/O Chip Selects do not compare the ...

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X OUT ADDR[23:0] DATA[7:0] (input) CSx MREQ RD INSTRD WAIT Chip Select Registers Chip Select x Lower Bound Register For Memory Chip Selects, the Chip Select x Lower Bound register, listed in page 56, defines the lower bound of the ...

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Table 18. Chip Select x Lower Bound Register (CS0_LBR = A8h, CS1_LBR = ABh, CS2_LBR Bit Reset CPU Access Note: R/W = Read/Write. Bit Position Value Description [7:0] 00h– For Memory Chip Selects (CS_io = 0) CS_LBR FFh This bit ...

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Bit Position Value Description [7:0] 00h– CS_UBR FFh Chip Select x Control Register The Chip Select x Control register, listed in the type of Chip Select, and sets the number of WAIT states. The reset state for the Chip Select ...

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Bit Position Value Description 3 0 CS_EN 1 [2:0] 000 PS006614-1208 Chip Select is disabled. Chip Select is enabled. Reserved—must be 000. eZ80190 Product Specification 58 Chip Selects and Wait States ...

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Random Access Memory The eZ80190 device features single-port data Random Access Memory (RAM) for general-purpose use and dual-port static RAM for use with the Multiply-Accumulator unit. Both RAM spaces can ...

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RAM Control Registers RAM Control Register The internal RAM spaces, data RAM and Multiply-Accumulator RAM, can be enabled by setting corresponding bits in this register. Table 21. RAM Control Register Bit Reset CPU Access Note: R/W = Read/Write. Bit Position ...

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Bit Position Value Description [7:0] 00h– RAM_ADDR_U FFh PS006614-1208 These bits define the upper byte of the RAM address. When on-chip general-purpose RAM is enabled, the general-purpose RAM address space ranges from {RAM_ADDR_U, E000h} to {RAM_ADDR_U, FFFFh}. When on-chip MACC ...

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... Universal Zilog Interface The eZ80190 device features two on-chip Universal Zilog Interface (UZI) devices. Each UZI contains three serial communication controller blocks: a Serial Peripheral Interface (SPI), a Universal Asynchronous Receiver/Transmitter (UART), and an Inter-Integrated Circuit serial bus (I trollers can be enabled. The UZI devices are connected to GPIO pins on Port C (UZI 1) and Port D (UZI 0) ...

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... Assert and deassert RESET • Set UARTx_LCTL[ enable access of the BRG divisor registers • Program the BRGx_DLR_L and BRGx_DLR_H registers PS006614-1208 Product Specification . On the next system clock ris- 0001h System Clock Frequency {BRGx_DLR_H, BRGx_DLR_L minimum BRG divisor 0002h Universal Zilog Interface eZ80190 device generates ...

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... CFh, UZI1_CTL = DFh Description All UZI devices are disabled. UART is enabled. SPI is enabled enabled. 0002h and as the values 0002h FFFFh 0000h eZ80190 Product Specification R/W R/W . The initial 16-bit divisor value and are invalid and 0001h UART Line Control Universal Zilog Interface 64 ...

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... BRG_DLR_L}. 0002h and because the values 0002h FFFFh D1h R/W R/W R/W R/W eZ80190 Product Specification R/W R/W R/W R/W . The initial 16-bit divisor value and are invalid, and 0000h 0001h UART Line Control R/W R/W R/W R/W Universal Zilog Interface 65 ...

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... Bit Position Value [7:0] 00h– BRG_DLR_H FFh PS006614-1208 Description These bits represent the High byte of the 16-bit Baud Rate Generator divider value. The complete BRG divisor value is returned by {BRG_DLR_H, BRG_DLR_L}. eZ80190 Product Specification 66 Universal Zilog Interface ...

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Universal Asynchronous Receiver/ Transmitter The UART module implements all of the logic required to support asynchronous commu- nications protocol. The module also implements two separate 16-byte FIFOs for both transmit and receive. A block diagram of the UART is displayed ...

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UART Functional Description The core uses an externally-provided clock from the Baud Rate Generator for the serial transmit/receive function. The UART module supports all of the various options in the asynchronous transmission and reception protocol including: • 8-bit ...

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The pro- cessor can reset this interrupt by loading data into the UARTx_THR register, which clears the transmitter interrupt. The transmit shift register ...

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UART Interrupts There are five different sources of interrupts from the UART. These five sources of inter- rupts are: 1. Transmitter 2. Receiver (three different interrupts) 3. Modem status UART Transmitter Interrupt The transmitter interrupt is generated if there is ...

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A line status interrupt is activated (provided this interrupt is enabled) as long as the read pointer of the receive FIFO points to the location of the FIFO that contains a byte with the error. The interrupt is immediately cleared ...

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Data Transfers To transmit data, the application enables the transmit interrupt. An interrupt is Transmit— immediately expected in response to this interrupt. The application reads the UARTx_IIR register and determines that the interrupt occurs because of an empty UARTx_THR regis- ...

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READ/WRITE attributes, reset conditions, and bit descriptions of all UART registers are provided in this section. UART Transmit Holding Register If less than eight bits are programmed for transmission, the lower bits of the byte ...

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Bit Position Value [7:0] 00h– RXD FFh UART Interrupt Enable Register The UARTx_IER register, listed in rupts. The UARTx_IER registers share the same I/O addresses as the BRGx_DLR_H reg- isters. Table 28. UART Interrupt Enable Registers Bit Reset CPU Access ...

Page 85

UART Interrupt Identification Register The Read Only UART Interrupt Identification register, listed in check the status of interrupts and whether the FIFO is enabled. These registers share the same I/O addresses as the UARTx_FCTL registers. Status codes for the UARTx_IIR ...

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UART FIFO Control Registers These registers, listed in and enable or disable the FIFO. The UARTx_FCTL registers share the same I/O addresses as the UARTx_IIR registers. Table 31. UART FIFO Control Registers Bit Reset CPU Access Note Write ...

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UART Line Control Register These registers, listed in ters. Table 33 on page 78 lists character length and stop bit parameters. Table 32. UART Line Control Registers Bit Reset CPU Access Note: R/W = Read/Write. Bit Position Value 7 0 ...

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Bit Position Value 3 0 PEN 1 [2:0] 000– CHAR 111 Table 33. UART Character Parameter Definition CHAR[2:0] 000 001 010 011 100 101 110 111 UART Modem Control Registers These registers are used to control and check the modem ...

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Bit Position Value [7:5] 000b 4 0 LOOP 1 3 0–1 OUT2 2 0–1 OUT1 1 0–1 RTS 0 0–1 DTR UART Line Status Registers These registers are used to show the status of UART interrupts and registers. Table 35. ...

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Bit Position Value 7 0 ERR TEMT THRE PS006614-1208 Description This bit is always 0 when operating with the FIFO disabled. ...

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Bit Position Value UART Modem Status Registers The UART Modem Status Registers, listed in UART signals. Table 36. UART Line Status Registers Bit Reset CPU Access Note Read Only. PS006614-1208 ...

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Bit Position Value 7 0–1 DCD 6 0– 0–1 DSR 4 0–1 CTS 3 0–1 DDCD 2 0–1 TERI 1 0–1 DDSR 0 0–1 DCTS UART Scratch Pad Registers The UARTx_SPR registers, listed in general-purpose Read/Write registers. PS006614-1208 ...

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Table 37. UART Line Control Registers Bit Reset CPU Access Note: R/W = Read/Write. Bit Position Value [7:0] 00h– SPR FFh PS006614-1208 (UART0_SPR = C7h, UART1_SPR = D7h R/W R/W R/W R/W ...

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... SPI devices serial peripheral interface, separate signals are required for data and clock. The eZ80190 device contains two SPI devices—one within each Universal Zilog Interface (UZI) block. The SPI devices may be configured as either master or slave. The connection ...

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When the SPI is not enabled by the UZI Control register, this signal oper- ates in a high-impedance state. Master Out Slave In The Master Out Slave In (MOSI) pin is configured as an output in a ...

Page 96

The master device always places data on the MOSI line a half-cycle before the clock edge (SCK signal), for the slave device to latch the data. SCK (CPOL bit = 0) ...

Page 97

MISO signal. The result is a full- duplex transmission, with both data out and data in synchronized with the same clock sig- nal. The byte transmitted is replaced by the ...

Page 98

The SCK signal then enters the IDLE state. In SPI SLAVE mode, the start logic receives a logic Low from the ...

Page 99

SPI Registers There are four registers in the Serial Peripheral Interface which provide control, status, and data storage functions. These registers are called the SPI Control register (SPIx_CTL), SPI Status register (SPIx_SR), SPI Receive Buffer register (SPIx_RBR), and SPI Transmit ...

Page 100

SPI Status Register The SPI Status Read Only register, listed in using the serial peripheral interface. Reading the SPIx_SR register clears bits 7, 6, and logical 0. Table 40. SPI Status Register Bit Reset CPU Access Note: ...

Page 101

Table 41. SPI Transmit Shift Register Bit Reset CPU Access Note Write Only. Bit Position Value Description 7 00h– TX_DATA FFh SPI Receive Buffer Register The SPI Receive Buffer register (SPIx_RBR) is used by the SPI slave to ...

Page 102

I C Serial I/O Interface I C General Characteristics 2 2 The I C serial I/O bus is a two-wire communication interface that can operate in four modes: 1. MASTER TRANSMIT 2. MASTER RECEIVE 3. SLAVE TRANSMIT 4. SLAVE ...

Page 103

Data Validity The data on the SDA line must be stable during the High period of the clock. The High or Low state of the data line can only change when the clock signal on the SCL line is Low, ...

Page 104

I C Acknowledge (ACK). Data is transferred with the msb first, see can hold the SCL line Low to force the transmitter into a WAIT state. Data transfer then continues when the receiver is ready for another byte of ...

Page 105

Data Output by Transmitter Data Output by Receiver SCL Signal From Master Clock Synchronization All masters generate their own clocks on the SCL line to transfer messages on the I Data is only valid during the High period of each ...

Page 106

Clk1 Signal Clk2 Signal SCL Signal Arbitration A master may start a transfer only if the bus is free. Two or more masters may generate a START condition within the minimum hold time of the START condition. The result is ...

Page 107

In other words, arbitration is not allowed between: • A repeated START condition and a data bit • A STOP condition and a data bit • A repeated START condition and a STOP condition Clock Synchronization for Handshake The Clock ...

Page 108

Table 43 Master Transmit Status Codes 2 Code I C State 18h Addr+W transmitted, ACK received 20h Addr+W transmitted, ACK not received 38h Arbitration lost 68h Arbitration lost, SLA+W received, ACK transmitted 78h Arbitration lost, General call ...

Page 109

Table 44 10-Bit Master Transmit Status Codes 2 Code I C State Arbitration lost 38h Arbitration lost, SLA+W 68h received, ACK transmitted Arbitration lost, SLA+R B0h received, ACK transmitted Second Address byte + D0h W transmitted, ACK ...

Page 110

Table 45 Master Transmit Status Codes For Data Bytes 2 Code I C State 28h Data byte transmitted, ACK received 30h Data byte transmitted, ACK not received 38h Arbitration lost When all bytes are transmitted, the microprocessor ...

Page 111

Table 46 Master Receive Status Codes 2 Code I C State 40h Addr + R transmitted, ACK received Addr + R transmitted, 48h ACK not received Arbitration lost 38h Arbitration lost, SLA+W 68h received, ACK transmitted Arbitration ...

Page 112

READ bit. The status code is then remains selected prior to the restart repeated START condition is received, the status code is After each data byte is received, the IFLG is set and ...

Page 113

I C goes from MASTER mode to SLAVE TRANSMIT mode when arbitration is lost dur- ing the transmission of an address, and the slave address and read bit are received. This action is confirmed by the status code The ...

Page 114

If the ACK bit is cleared to 0 during a transfer, the I on SDA) after the next byte is received, and sets the IFLG bit. The tains the status code call address. The Registers 2 Addressing ...

Page 115

I C Slave Address Register The I2Cx_SAR register, indicated in SLAVE mode and allows 10-bit addressing in conjunction with the I2Cx_xSAR register. I2Cx_SAR[7:1] = SLA[6:0] is the 7-bit address of the I 2 When the I C receives this ...

Page 116

Table 50 Extended Slave Address Registers Bit Reset CPU Access Note: R/W = Read/Write. Bit Position Value Description [7:0] 00h– SLAX FFh Data Register 2 The I C Data Register, listed in mitted or ...

Page 117

When the Bus Enable bit (ENAB) is set to 0, the I 2 and the I C module does not respond to any address on the bus. When ENAB is set the I C responds to calls ...

Page 118

Table 52 Control Registers Bit Reset CPU Access Note: R/W = Read/Write. Bit Position Value Description 7 0 IEN ENAB STA STP IFLG 1 2 ...

Page 119

Table 53 Status Registers Reset CPU Access Note Read Only. Bit Position Value [7:3] 00000– STAT 11111 [2:0] 000 There are 29 possible status codes, listed in the status code F8h and the IFLG bit ...

Page 120

Table 54 Status Codes (Continued) Code Status Arbitration lost in address as master, slave address + write bit received, ACK 68h transmitted 70h General Call address received, ACK transmitted 78h Arbitration lost in address as master, General ...

Page 121

Table 55 Clock Control Registers Bit Reset CPU Access Note Read Only. Bit Position Value 7 0 [6:3] 0000– M 1111 [2:0] 000–111 The I C clocks are derived by the eZ80190 ...

Page 122

To ensure correct detection of START and STOP conditions on the bus, the I 2 ple the I C bus at least ten times faster than the bus clock speed of the fastest master on the bus. The sampling frequency ...

Page 123

Multiply-Accumulator MACC Overview The most significant process in digital signal processing is the Multiply-Accumulate (MACC) function, which forms a sum of products, as the following equation shows. n ∑ × where x and y are ...

Page 124

Multiply-Accumulator Basic Operation Figure 22 on page 115 displays a simplified view of the state progression of the MACC when performing calculation on a set of data. The progression begins in the upper left cor- ner with a DATA bank ...

Page 125

DATA Bank EMPTY ® The eZ80 can define a new calculation for the MACC. Read DATA Bank Accumulator DATA Bank DONE CALC Bank swapped with DATA Bank. Result ready in accumulator. Software Control of the MACC The Multiply-Accumulator is designed ...

Page 126

Depending upon the number of bytes of result required, the INI2R instruction can read all 5 of the MACC_ACx registers or as few as 1. The Multiply-Accumulator decodes its I/O addresses from ADDR[7:0]. In addition, it monitors ADDR[15:8] to ...

Page 127

Alternatively, any write operation to any of the MACC registers besides MACC_STAT also changes the DATA bank status from DONE to EMPTY. This state change occurs because write operations generally indicate a requirement to define a new calculation. Alternatives to ...

Page 128

Table 57. MACC DATA Bank Status Codes (Continued) DATA Bank Status MACC_STAT[1:0] Description 01b The DATA bank is READY. Calculation is prepared for execution as soon as the MACC is ready to begin a new calculation. 10b Invalid. 11b The ...

Page 129

Table 59. State Progression of the MACC During Operation Current State DATA CALC Bank Bank EMPTY EMPTY 1. Define a new calculation by loading the MACC control registers using the OTI2R instruction. When the OTI2R instruction completes and the final ...

Page 130

Table 59. State Progression of the MACC During Operation (Continued) Current State DATA CALC Bank Bank EMPTY DONE 1. Define a new calculation by loading the MACC control registers using the OTI2R instruction. When the OTI2R instruction completes and the ...

Page 131

Table 59. State Progression of the MACC During Operation (Continued) Current State DATA CALC Bank Bank DONE IN If the MACC completes execution of the current PROGRESS calculation, the CALC bank status changes from IN PROGRESS to DONE. DONE IN ...

Page 132

When IN_SHIFT = Example 1— not shifted. If the MACC Accumulator is loaded with a 40-bit value using a succession of 8-bit writes, the procedure appears as follows: 1. Write the LSB to the MACC Accumulator MACC Accumulator [7:0] = ...

Page 133

OUT_SHIFT Function The OUT_SHIFT field, bits 5:3 of the MACC_CTL register, defines the magnitude of the right-shift that is performed when the CPU reads a result from the MACC Accumulator registers MACC_AC0, MACC_AC1, MACC_AC2, MACC_AC3, and MACC_AC4. The MACC automatically ...

Page 134

Read the fourth byte from the MACC Accumulator DATA_OUT[7:0] = MACC_AC3[7:0] = MACC Accumulator [34:27] 5. Read the MSB from the MACC Accumulator DATA_OUT[7:0] = MACC_AC4[7:0] = {000b, MACC Accumulator [39:35]} In Example 2, notice that the upper 3 ...

Page 135

If the DATA bank status is EMPTY and the CALC bank status is DONE, write the status register result, the register banks are swapped so that the DATA status becomes DONE both status fields indicate ...

Page 136

MACC_xEND and MACC_yEND define the end of the linear address space for the x and y data, respectively. After either the ending value is reached, the next address is defined by MACC_xRELOAD or MACC_yRELOAD, respectively. 3. ...

Page 137

MACC Registers _x MACC START _x MACC END _x MACC RELOAD MACC_LENGTH Multiply-Accumulator Control And Data Registers The MACC is divided into two separate operating banks. The CPU can only access the current DATA bank via the control and data ...

Page 138

Table 60. MACC x DATA Starting Address Register Reset CPU Access Note: R/W = Read/Write. Bit Position Value Description [7:0] 00h– MACC_xSTART FFh MACC DATA Ending Address Register x The MACC xEND register, listed read 16-bit values ...

Page 139

Bit Position Value Description [7:0] 00h– MACC_xRELOAD FFh MACC Length Register The MACC_LENGTH register, listed in pairs that are multiplied and accumulated for the MACC operation. Table 63. MACC Length Register Bit Reset CPU Access Note: R/W = Read/Write. Bit ...

Page 140

MACC DATA Ending Address Register y The MACC_yEND register, listed in the MACC to read 16-bit values from the y DATA for performing its calculations. Table 65. MACC y DATA Ending Address Register Bit Reset CPU Access Note: R/W = ...

Page 141

Table 67. MACC Control Register Bit Reset CPU Access Note: R/W = Read/Write. Bit Position Value Description 7 0 MACC interrupt is disabled. MACC_IE 1 The MACC interrupt is enabled for the calculation currently being defined. The MACC generates an ...

Page 142

Bit Position Value Description [2:0] 000 No left-shift is performed during writes to the MACC Accumulator IN_SHIFT registers by the CPU. MACC_ACx[39:0] = DATA_IN[39:0] 001 Writes to the MACC Accumulator registers by the CPU are left- shifted by 1 bit ...

Page 143

Bit Position Value Description [7:0] 00h– MACC_AC0 FFh MACC Accumulator Byte 1 Register The MACC_AC1 register, listed in mulator. Table 69. MACC Accumulator Byte 1Register Bit Reset CPU Access Note Undefined; R/W = Read/Write. Bit Position Value Description ...

Page 144

MACC Accumulator Byte 3 Register The MACC_AC3 register, listed in Accumulator. Table 71. MACC Accumulator Byte 3 Register Bit Reset CPU Access Note Undefined; R/W = Read/Write. Bit Position Value Description [7:0] 00h– MACC_AC3 FFh MACC Accumulator Byte ...

Page 145

MACC Status Register The MACC_STAT register, listed in Accumulator. Writing a value of has completed its calculation (DONE) and the DATA register is not loaded with a new cal- culation (EMPTY) swaps the banks to allow the pending result to ...

Page 146

Bit Position Value Description [1:0] 00 DATA_STAT PS006614-1208 The DATA bank is EMPTY. No calculation is set up for execution. The DATA bank is READY. The calculation is prepared for execution. Invalid. The DATA bank is DONE. ...

Page 147

Interrupt Controller The interrupt controller on the eZ80190 device routes the interrupt request signals from the internal peripherals and external devices (via the internal port I/O) to the eZ80 On the eZ80190 device, all interrupts use the CPU’s vectored interrupt ...

Page 148

Table 75. Vectored Interrupt Operation Memory ADL MADL Mode Bit Bit Operation ® Z80 Mode 0 0 Read the LSB of the interrupt vector placed on the internal vectored interrupt bus, IVECT [7:0], by the interrupting peripheral. • IEF1 • ...

Page 149

Table 75. Vectored Interrupt Operation (Continued) ® Z80 Mode 0 1 Read the LSB of the interrupt vector placed on the internal vectored interrupt bus, IVECT[7:0], bus by the interrupting peripheral. • IEF1 • IEF2 • The Starting Program Counter ...

Page 150

Direct Memory Access Controller The eZ80190 device features two Direct Memory Access (DMA) channels. The DMA controller can be used for direct memory to memory data transfers without CPU interven- tion. There are two DMA channels, Channel 0 and Channel ...

Page 151

DMA Transfer Modes There are two modes of operation for the DMA channels. The DMA can transfer data in BURST mode or CYCLE-STEAL mode. The data transfer mode is controlled by the BURST bit in the DMA Control registers (DMAx_CTL[4]). ...

Page 152

DMA Channel Priorities In all operating mode combinations, DMA Channel 0 is prioritized higher than DMA Channel 1. If Channel 0 is configured for BURST mode operation, Channel 0 completes its entire block transfer before Channel 1 begins its transfer. ...

Page 153

Table 76. DMA Registers (Continued) Name Description DMA0_DAR_L DMA0 Destination Address Low Byte register DMA0_DAR_H DMA0 Destination Address High Byte register DMA0_DAR_U DMA0 Destination Address Upper Byte register DMA0_BC_L DMA0 Byte Count Low Byte register DMA0_BC_H DMA0 Byte Count High ...

Page 154

Bit Position Value Description [7:0] 00h– DMAx_SAR_L, FFh DMAx_SAR_H, or DMAx_SAR_U DMA Destination Address Registers This group of registers holds the 24-bit address of the current destination memory loca- tion. Depending upon settings within the DMA Control registers’ DMA_CTL fields, ...

Page 155

Table 79. DMA Byte Count Registers DMA0_BC_L = F4h, DMA0_BC_H = F5h, DMA1_BC_L = Bit Reset CPU Access Note: R/W = Read/Write. Bit Position Value Description [7:0] 00h– DMAX_BC_L FFh or DMAX_BC_H DMA Control Registers Table 80 lists the control ...

Page 156

Bit Position Value Description [3:2] 00 DAR_CTL [1:0] 00 SAR_CTL PS006614-1208 The destination address is unchanged following the transfer of each byte. The destination address increments following the transfer of each byte. The destination ...

Page 157

... C source-level debugging using Zilog Developer Studio II (ZDS II) The above features are built into the silicon. Control is provided via a two-wire interface that is connected to the ZPAK II emulator. get board, ZPAK II, and the host PC running Zilog Developer Studio. For more informa- tion on ZPAK II and ZDS II, refer to www.zilog.com. Zilog ...

Page 158

... All information is passed between the master and the slave in 8-bit (single-byte) units. Each byte is transferred with nine clock cycles: eight to shift the data, and the ninth for internal operations. PS006614-1208 330K 330K 6-Pin Target Connector eZ80190 Product Specification TV DD (Target Zilog Debug Interface 148 ...

Page 159

... Figure 28. ZDI Write Timing ZDI Data Out (read) ZDA ZDA ZDA Change Stable Change Figure 29. ZDI Read Timing eZ80190 Product Specification and Figure 29 display a valid ZDA ZDA Stable Change ZDI Data Out (read) ZDA ZDA Stable Change Zilog Debug Interface 149 ...

Page 160

... Product ID Low Byte while a write to this same location, Figure 30 displays the timing for address writes to ZDI registers. ZDI Address Byte Figure 30. ZDI Address Write Timing eZ80190 Product Specification th bit. For most ZDI oper- Single-Bit Byte Separator or new ZDI START Signal R/W 1 lsb 0 = write 1 = read Zilog Debug Interface 150 ...

Page 161

... ZDI block WRITE operations. PS006614-1208 ZDI Data Byte msb of DATA Figure 31. ZDI Single-Byte Data Write Timing 30h eZ80190 Product Specification Figure lsb of DATA end of data or new ZDI START signal ), the address stops incrementing. Zilog Debug Interface 151 ...

Page 162

... Figure 32. ZDI Block Data Write Timing Figure 33 displays the timing for ZDI single-byte ZDI Data Byte msb of DATA Figure 33. ZDI Single-Byte Data Read Timing eZ80190 Product Specification msb of DATA byte 2 1-bit data separator lsb of DATA End of data or new ZDI START signal Zilog Debug Interface 152 ...

Page 163

... ZDI Read Only registers. PS006614-1208 Figure 34 displays ZDI block READ timing. ZDI Data Bytes msb lsb of of DATA DATA byte 1 byte 1 Figure 34. ZDI Block Data Read Timing eZ80190 Product Specification ), the address 20h msb of DATA byte 2 1-bit data separator Zilog Debug Interface 153 ...

Page 164

... Product Specification 154 Reset Value Page # 156 XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh 156 00h 159 XXh 159 XXh 159 XXh 160 00h 161 XXh XXh XXh XXh XXh 162 XXh Zilog Debug Interface ...

Page 165

... Read Memory Address Upper Byte register Read Memory Data Value ® mode, the address is provided by eZ80190 Product Specification 155 Reset Value Page # 163 05h 163 00h 164 XXh 164 00h 165 XXh 165 XXh 165 XXh 166 XXh Zilog Debug Interface ...

Page 166

... This function only breaks on the first Op Code in a multiple Op Code instruction. If both the ZCL and ZDA pins are forced Low (0) during a RESET, this bit is set to 1 and a break occurs on the first instruction following the RESET. eZ80190 Product Specification Zilog Debug Interface 156 ...

Page 167

... Breaks can only occur on an instruction boundary. If the address is not the beginning of an instruction, then the break occurs at the end of the current instruction. The break is implemented by setting the BRK_NEXT bit to 1. The BRK_NEXT bit must be reset release the break. eZ80190 Product Specification 157 Zilog Debug Interface ...

Page 168

... ADDR[23:8], match the 2 bytes value {ZDI_ADDR0_U, ZDI_ADDR0_H result, a break can occur anywhere within a 256-byte page. ZDI SINGLE STEP mode is disabled. ZDI SINGLE STEP mode is enabled. ZDI asserts a break following execution of each instruction. eZ80190 Product Specification 158 Zilog Debug Interface ...

Page 169

... The 24-bit data value is stored as {ZDI_WR_U, ZDI_WR_H, ZDI_WR_L}. If less than 24 bits of data are required to complete the required operation, the data is taken from the LSB(s). Table 86 eZ80190 Product Specification Table 86 on page 160 page 160. When a read opera- Zilog Debug Interface 159 ...

Page 170

... IXH ← ZDI_WR_L IXL 85 Write IY ← ZDI_WR_U IYU ← ZDI_WR_H IYH ← ZDI_WR_L IYL 86 Write SP In ADL mode SPL. In Z80 mode SPS. 87 Write PC ← ZDI_WR_U PC[23:16] ← ZDI_WR_H PC[15:8] ← ZDI_WR_L PC[7:0] 88 Reserved 89 Reserved eZ80190 Product Specification 160 Zilog Debug Interface ...

Page 171

... Command 8A Reserved 8B Write memory from current PC value, increment PC Table 87, are located in the ZDI Register ® CPU instructions, when combined with the MEMORY mode suf- (ZDI_IS4 = 21h, ZDI_IS3 = 22h, ZDI_IS2 = 23h, ZDI_IS1 = 24h, ZDI_IS0 = 25h eZ80190 Product Specification Zilog Debug Interface 161 ...

Page 172

... The program counter is incremented following each 8-bits of data. In Z80 MEMORY mode, ({MBASE, ← PC[15:0]}) 8 bits of transferred data. In ADL MEMORY ← mode, (PC[23:0]) 8-bits of transferred data. }. eZ80190 Product Specification Table 88, causes the eZ80190 device Table 89 on page 163, combine to Zilog Debug Interface 162 ...

Page 173

... This number is changed for each revision. PS006614-1208 Address Space {ZDI_ID_H, ZDI_ID_L} = {00h, 05h} indicates the eZ80190 product. Only Address Space {ZDI_ID_H, ZDI_ID_L} = {00h, 05h} indicates the product. Table 91, identifies the current revision of the eZ80190 Product Specification Table 90, combine to provide eZ80190 Zilog Debug Interface 163 ...

Page 174

... The CPU is operating in Z80 MEMORY mode (ADL bit flag = 0). The CPU is operating in ADL MEMORY mode (ADL bit flag = 1). The CPU’s Mixed-Memory mode (MADL) bit is reset to 0. The CPU’s Mixed-Memory mode (MADL) bit is set to 1. eZ80190 Product Specification Zilog Debug Interface 164 ...

Page 175

... Reserved—must be 0. (ZDI_RD_L = 10h, ZDI_RD_H = 11h, ZDI_RD_U = 12h Values read from the memory location as requested by the ZDI Read Control register during a ZDI read operation. The 24-bit value is stored in {ZDI_RD_U, ZDI_RD_H, ZDI_RD_L}. eZ80190 Product Specification Table 93 ® mode, Zilog Debug Interface 165 ...

Page 176

... PS006614-1208 Only Address Space 8-bit data read from the memory address indicated by the CPU’s program counter. In Z80 mode, 8-bit data ← transferred out ({MBASE, SPS}). In ADL mode, 8-bit ← data transferred out (SPL). eZ80190 Product Specification Zilog Debug Interface 166 ...

Page 177

CPU Instruction Set Table 95 through eZ80190 device. The instructions are grouped by class. More detailed information is avail- ® able in eZ80 CPU User Manual (UM0077). Note: The Sleep (SLP) instruction is not supported on the eZ80190 ...

Page 178

Table 97. Block Transfer and Compare Instructions Mnemonic CPD (CPDR) CPI (CPIR) LDD (LDDR) LDI (LDIR) Table 98. Exchange Instructions Mnemonic EX EXX Table 99. Input/Output Instructions Mnemonic IN IN0 IND (INDR) IND2 (IND2R) INDM (INDMR) INI (INIR) INI2 (INI2R) ...

Page 179

Table 99. Input/Output Instructions (Continued) Mnemonic OUTI (OTIR) OUTI2 (OTI2R) TSTIO Table 100. Load Instructions Mnemonic LD LEA PEA POP PUSH Table 101. Logical Instructions Mnemonic AND CPL OR TST XOR Table 102. Processor Control Instructions Mnemonic CCF DI EI ...

Page 180

Table 102. Processor Control Instructions (Continued) Mnemonic IM NOP RSMIX SCF SLP STMIX Table 103. Program Control Instructions Mnemonic CALL CALL cc DJNZ RET RET cc RETI RETN RST Table 104. Rotate and Shift ...

Page 181

Table 104. Rotate and Shift Instructions (Continued) Mnemonic RLCA RLD RR RRA RRC RRCA RRD SLA SRA SRL PS006614-1208 Instruction Rotate Left Circular–Accumulator Rotate Left Decimal Rotate Right Rotate Right–Accumulator Rotate Right Circular Rotate Right Circular–Accumulator Rotate Right Decimal Shift ...

Page 182

Op-Code Map Table 105 through tions. Table 105. Op Code Map—First Op Code Lower Op Code Nibble Legend Upper Op Code 4 Nibble AND Mnemonic A A,H Second Operand First Operand NOP LD LD INC ...

Page 183

Table 106. Op Code Map—Second Op Code after 0CBh Legend Lower Nibble of 2nd Op Code Upper Nibble 4 of Second RES Mnemonic Op Code A 4,H Second Operand First Operand RLC RLC RLC RLC ...

Page 184

Table 107. Op Code Map—Second Op Code After 0DDh L EGEND OWER IBBLE PPER 9 N IBBLE S OF ECOND LD M NEMONIC ODE SP, ECOND IRST ...

Page 185

Table 108. Op Code Map—Second Op Code After 0EDh Legend Lower Nibble of 2nd Op Code Upper 2 Nibble of Second SBC Mnemonic 4 Op Code HL,BC First Operand Second Operand IN0 OUT0 LEA LEA ...

Page 186

Table 109. Op Code Map—Second Op Code After 0FDh Legend Lower Nibble of 2nd Op Code Upper 9 Nibble of Second LD Mnemonic F Op Code SP,IY First Operand Second Operand ...

Page 187

Table 110. Op Code Map—Fourth Byte After 0DDh, 0CBh, and dd Legend Lower Nibble of 4th Byte Upper Nibble 6 of Fourth BIT Mnemonic 4 Byte 0,(IX+d) First Operand Second Operand ...

Page 188

Table 111. Op Code Map—Fourth Byte After 0FDh, 0CBh, and dd Legend Lower Nibble of 4th Byte Upper Nibble 6 of Fourth BIT Mnemonic Byte 4 0,(IY+d) First Operand Second Operand ...

Page 189

Crystal Oscillator The eZ80190 device features an on-chip crystal oscillator that supplies clocks to the inter- ® nal eZ80 CPU core, to peripherals, and to the external pin. The clock circuitry uses the three dedicated pins X The external clock/oscillator ...

Page 190

Electrical Characteristics Absolute Maximum Ratings Stresses greater than those listed in These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute ...

Page 191

DC Characteristics Table 113 lists the Direct Current characteristics of the eZ80190 device. Table 113. DC Characteristics Temperature Range Symbol Parameter V Supply Voltage DD V Low Level IL Input Voltage V High Level 0 Input Voltage ...

Page 192

PS006614-1208 ICC vs. WAIT States (Typical @ 3.3V, 25C Figure 36. I vs. WAIT1 CC ICC vs ...

Page 193

PS006614-1208 ICC vs. Frequency (Typical @3.3V, 25C Frequency (MHz) Figure 38. I vs. Frequency CC ICC vs. Temp (Typical @ 3.3V, 7 WAIT States) 80.00 ...

Page 194

AC Characteristics The section provides information on the Alternating Current (AC) characteristics and tim- ing of the eZ80190 device. All AC timing information assumes a standard load all outputs. Table 114. AC Characteristics T Symbol Parameter ...

Page 195

External Memory Read Timing Figure 40 and Table 115 ADDR[23:0] DATA[7:0] (input) CSx T 7 MREQ Figure 40. External Memory Read Timing Table 115. External Read Timing Parameter Description T Clock Rise to ADDR ...

Page 196

Table 115. External Read Timing (Continued) Parameter Description T Clock Rise to MREQ Deassertion Delay 8 T Clock Rise to RD Assertion Delay 9 T Clock Rise to RD Deassertion Delay 10 External Memory Write Timing Figure 41 and Table ...

Page 197

Table 116. External Write Timing Parameter Description T Clock Rise to ADDR Valid Delay 1 T Clock Rise to ADDR Hold Time 2 T Clock Rise to Output DATA Valid Delay 3 T DATA Hold Time from Clock Rise 4 ...

Page 198

External I/O Read Timing Figure 42 and Table 117 X IN ADDR[23:0] DATA[7:0] (input) CSx T IORQ T RD Figure 42. External I/O Read Timing Table 117. External I/O Read Timing Parameter Description T Clock Rise to ADDR Valid Delay ...

Page 199

Table 117. External I/O Read Timing (Continued) Parameter Description T Clock Rise to RD Assertion Delay 9 T Clock Rise to RD Deassertion Delay 10 External I/O Write Timing Figure 43 and Table 118 X IN ADDR[23:0] DATA[7:0] (output) CSx ...

Page 200

Table 118. External I/O Write Timing Parameter Description T Clock Rise to ADDR Valid Delay 1 T Clock Rise to ADDR Hold Time 2 T Clock Rise to Output DATA Valid Delay 3 T DATA Hold Time from Clock Rise ...

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