IC 33MHZ STATIC MIMIC 100-LQFP

Z8018233ASG

Manufacturer Part NumberZ8018233ASG
DescriptionIC 33MHZ STATIC MIMIC 100-LQFP
ManufacturerZilog
Z8018233ASG datasheet
 


Specifications of Z8018233ASG

Processor TypeZ180FeaturesSmart Peripheral Controller
Speed33MHzVoltage5V
Mounting TypeSurface MountPackage / Case100-LQFP
Processor SeriesZ8018xxCoreZ80
Data Bus Width8 bitProgram Memory TypeROMLess
Interface TypeUARTMaximum Clock Frequency33 MHz
Number Of Programmable I/os24Number Of Timers2
Operating Supply Voltage4.5 V to 5.5 VMaximum Operating Temperature+ 70 C
Mounting StyleSMD/SMTMinimum Operating Temperature0 C
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Zilog
FEATURES
Z8S180 MPU
- Code Compatible with Zilog Z80
- Extended Instructions
- Operating Frequency: 33 MHz/5V or 20 MHz/3.3V
- Two DMA Channels
- On-Chip Wait State Generators
- Two UART Channels
- Two 16-Bit Timer Counters
- On-Chip Interrupt Controller
- On-Chip Clock Oscillator/Generator
- Clocked Serial I/O Port
- Fully Static
- Low EMI Option
GENERAL DESCRIPTION
The Z80182/Z8L182 is a smart peripheral controller IC for
modem (in particular V. Fast applications), fax, voice
messaging and other communications applications. It
uses the Z80180 microprocessor (Z8S180 MPU core)
linked with two channels of the industry standard Z85230
ESCC (Enhanced Serial Communications Controller), 24
bits of parallel I/O, and a 16550 MIMIC for direct connection
to the IBM PC, XT, AT bus.
The Z80182/Z8L182 allows complete flexibility for both
internal PC and external applications. Also current PC
modem software compatibility can be maintained with the
Z80182/Z8L182 ability to mimic the 16550 UART chip. The
Z80180 acts as an interface between the ESCC
16550 MIMIC interface when used in internal applications,
and between the two ESCC channels in the external
applications. This interface allows data compression and
DS971820600
P R E L I M I N A R Y
P
RELIMINARY
Z80182/Z8L182
Z
I
ILOG
NTELLIGENT
C
ONTROLLER
Two ESCC
®
/Z180
CPU
Three 8-Bit Parallel I/O Ports
16550 Compatible MIMIC Interface for
Direct Connection to PC, XT, AT Bus
100-Pin Package Styles (QFP, VQFP)
(0.8 Micron CMOS 5120 Technology)
Individual WSG for RAMCS and ROMCS
error correction on outgoing and incoming data. In external
applications, three 8-bit parallel ports are available for
driving LEDs or other devices. Figure 1 shows the Z80182/
Z8L182 block diagram, while the pin assignments for the
QFP and the VQFP packages are shown in Figures 2 and
3, respectively. All references in this document to the
Z80182, or Z182 refer to both the Z80182 and Z8L182.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
and
Connection
Power
Ground
PS009801-0301
Z80182/Z8L182
Z
I
P
ILOG
NTELLIGENT
ERIPHERAL
P
S
RODUCT
PECIFICATION
P
ERIPHERAL
(ZIP
)
Channels with 32-Bit CRC
Circuit
Device
V
V
CC
DD
V
GND
SS
3-1

Z8018233ASG Summary of contents

  • Page 1

    ... Zilog FEATURES Z8S180 MPU - Code Compatible with Zilog Z80 - Extended Instructions - Operating Frequency: 33 MHz/ MHz/3.3V - Two DMA Channels - On-Chip Wait State Generators - Two UART Channels - Two 16-Bit Timer Counters - On-Chip Interrupt Controller - On-Chip Clock Oscillator/Generator - Clocked Serial I/O Port - Fully Static ...

  • Page 2

    ... Zilog GENERAL DESCRIPTION (Continued) D7-D0 Control A19-A0 Bus Transceiver Tx Data 85230 ESCC Rx Data Channel A ESCC Control /ROMCS Address Decode /RAMCS 8-Bit Parallel Port C MUX 85230 ESCC Ch Port C Z180 Signals or Port B Note: Conventional use of the term "MPU side" refers to all interface through the Z180 MPU core and " ...

  • Page 3

    ... Zilog 100 /INT0 1 /INT1/PC6 /INT2/PC7 A10 15 A11 A12 VSS A13 A14 20 A15 A16 A17 A18/TOUT VDD 25 A19 Figure 2. Z80182/Z8L182 100-Pin QFP Pin Configuration DS971820600 Z80182/Z8L182 100-Pin QFP PS009801-0301 Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL 80 /TRXCB/HA0 TXDB//HDDIS /CTSB//HWR /DCDB//HRD TXDA 75 /TRXCA ...

  • Page 4

    ... Zilog GENERAL DESCRIPTION (Continued) 75 TXDB//HDDIS 76 /TRXCB/HA0 RXDB/HA1 /RTXCB/HA2 /SYNCB//HCS 80 /HALT /RFSH /IORQ /MRD//MREQ E 85 /M1 /WR /RD PHI VSS 90 XTAL EXTAL /WAIT /BUSACK /BUSREQ 95 /RESET /NMI /INT0 /INT1/PC6 /INT2/PC7 100 1 Figure 3. Z80182/Z8L182 100-Pin VQFP Pin Configuration 3 Z80182/Z8L182 100-Pin VQFP 5 10 ...

  • Page 5

    ... Zilog Z180 CPU SIGNALS A19-A0. Address Bus (input/output, active High, tri-state). A19-A0 form a 20-bit address bus. The Address Bus provides the address for memory data bus exchanges Mbyte, and I/O data bus exchanges up to 64K. The address bus enters a high impedance state during reset and external bus acknowledge cycles, as well as during SLEEP and HALT states ...

  • Page 6

    ... Zilog Z180 CPU SIGNALS (Continued) /NMI. Non-maskable interrupt (input, negative edge triggered). /NMI has a higher priority than /INT and is always recognized at the end of an instruction, regardless of the state of the interrupt enable flip-flops. This signal forces CPU execution to continue at location 0066H. /INT0. Maskable Interrupt Request 0 (input/output active Low) ...

  • Page 7

    ... Zilog Z180 MPU DMA SIGNALS /TEND0. Transfer End 0 (output, active Low). This output is asserted active during the last write cycle of a DMA operation used to indicate the end of the block transfer. /TEND0 is multiplexed with CKA1 on the CKA1//TEND0 pin. /TEND1. Transfer End 1 (output, active Low). This output is asserted active during the last write cycle of a DMA operation ...

  • Page 8

    ... Zilog Z85230 ESCC SIGNALS (Continued) /SYNCA, /SYNCB. Synchronization (inputs/outputs, active Low). These pins can act as either inputs, outputs part of the crystal oscillator circuit. In the Asynchronous Receive mode (crystal oscillator option not selected), these pins are inputs similar to /CTS and /DCD. In this ...

  • Page 9

    ... Zilog /W//REQB. Wait/Request (output, open drain when programmed for the Wait function, driven High or Low when programmed for a Request function). This pin is similar in functionality to /W//REQA but is applicable on 16550 MIMIC INTERFACE SIGNALS HD7-HD0. Host Data Bus (input/output, tri-state). In Z80182/ Z8L182 mode 1, the host data bus is used to communicate between the 16550 MIMIC interface and the PC/XT/AT ...

  • Page 10

    ... Zilog EMULATION SIGNALS EV1, EV2. Emulation Select (input). These two pins determine the emulation mode of the Z180 MPU (Table 1). Mode EV2 SYSTEM CONTROL SIGNALS ST. Status (output, active High). This signal is used with the /M1 and /HALT output to decode the status of the CPU machine cycle ...

  • Page 11

    ... Zilog MULTIPLEXED PIN DESCRIPTIONS A18/T During Reset, this pin is initialized as an A18 pin. OUT. If either TOC1 or TOC0 bit of the Timer Control Register (TCR) is set to 1, The T function is selected. If TOC1 and OUT TOC0 bits are cleared to 0, the A18 function is selected. In normal user mode (on-chip bus master), the A18 signal ...

  • Page 12

    ... Zilog Ports B and C Multiplexed Pin Descriptions Ports B and C are pin multiplexed with the Z180 ASCI functions and part of ESCC channel A. The MUX function is controlled by bits 7-5 in the System Configuration Register. The MUX is organized as shown in Table 4. Table 4. Multiplexed Port Pins Port Mode ...

  • Page 13

    ... Zilog Table 5. Primary, Secondary and Tertiary Pin Functions Pin Number 1st VQFP QFP Function A10 13 16 A11 14 17 A12 A13 17 20 A14 18 21 A15 19 22 A16 20 23 A17 21 24 A18/T OUT A19 /RTS0 33 36 /CTS0 34 37 /DCD0 35 38 TxA0 36 39 RxA0 ...

  • Page 14

    ... Zilog MULTIPLEXED PIN DESCRIPTIONS (Continued) Table 5. Primary, Secondary and Tertiary Pin Functions (Continued) Pin Number 1st VQFP QFP Function CKA1//TEND0 43 46 TxS 44 47 CKS 45 48 /DREQ1 /TEND1 48 51 /RAMCS 49 52 /ROMCS 50 53 EV1 51 54 EV2 52 55 PA0 53 56 PA1 54 57 ...

  • Page 15

    ... Zilog Table 5. Primary, Secondary and Tertiary Pin Functions (Continued) Pin Number 1st VQFP QFP Function 71 74 RxDA 72 75 /TRxCA 73 76 TxDA 74 77 /DCDB 75 78 /CTSB 76 79 TxDB 77 80 /TRxCB 78 81 RxDB 79 82 /RTxCB 80 83 /SYNCB 81 84 /HALT 82 85 /RFSH 83 86 /IORQ ...

  • Page 16

    ... Therefore, for a detailed description of each individual unit, refer to the Z182 MPU FUNCTIONAL DESCRIPTION This unit provides all the capabilities and pins of the Zilog Z8S180 MPU (Static Z80180 MPU). Figure 4 shows the S180 MPU Block Diagram of the Z182. This allows 100% Timing & ...

  • Page 17

    ... Zilog Z182 CPU The Z182 CPU is 100% software compatible with the Z80 CPU and has the following additional features: Faster Execution Speed. The Z182 CPU is “fine tuned,” making execution speed, on average, 10% to 20% faster than the Z80 CPU. Enhanced DRAM Refresh Circuit. Z182 CPU’s DRAM refresh circuit does periodic refresh and generates an 8-bit refresh address ...

  • Page 18

    ... Zilog ™ Z85230 ESCC FUNCTIONAL DESCRIPTION The Zilog Enhanced Serial Communication Controller ™ ESCC is a dual channel, multiprotocol data communication peripheral. The ESCC functions as a serial-to-parallel, parallel-to-serial converter/controller. The ESCC can be software-configured to satisfy a wide variety of serial communications applications. The device contains a variety ...

  • Page 19

    ... Zilog The following features are common to both the ESCC and the CMOS SCC: Two independent full-duplex channels Synchronous/Isochronous data rates 1/4 of the PCLK using external clock source - Mbits/sec at 20 MHz PCLK (ESCC). Asynchronous capabilities - bits/character (capable of handling 4 bits/character or less 1. stop bits ...

  • Page 20

    ... Zilog ™ Z85230 ESCC BLOCK DIAGRAM For a detailed description of the Z85230 ESCC, refer to the ESCC Technical Manual. The following figure is the block diagram of the discrete ESCC, which was integrated into the Z182. The /INT line is internally connected to "INTO of the Z182. Channel A ...

  • Page 21

    ... Zilog 16550 MIMIC INTERFACE FUNCTIONAL DESCRIPTION The Z80182/Z8L182 has a 16550 MIMIC interface that allows it to mimic the 16550 device. It has all the interface pins necessary to connect to the PC/XT/AT bus. It contains the complete register set of the part with the same interrupt structure. The data path allows parallel transfer of data to and from the register set by the internal Z80180 of the Z80182/Z8L182 ...

  • Page 22

    ... Zilog 16550 MIMIC FIFO DESCRIPTION The receiver FIFO consists of a 16-word FIFO capable of storing eight data bits and three error bits for each character stored (Figure 7). Parity error, Framing error and Break detect bits are stored along with the data bits by copying their value from three shadow bits that are Write Only bits for the Z80180 MPU LSR address ...

  • Page 23

    ... Zilog Error Description Error in At least one data byte available RCVR in FIFO with one error FIFO *TEMT Transmitter empty † *THRE Transmitter holding register is empty Break Break occurs when Detect received data input is held in logic-0 for longer than a full word transmission ...

  • Page 24

    ... Zilog 16550 MIMIC FIFO DESCRIPTION (Continued) The PC interface may be interrupted when bytes are available in the receiver FIFO by setting bits 6 and 7 in the FCR (FIFO Control Register, PC address 02H) to the appropriate value. If the FIFO is not empty, but below the above trigger value, a timeout interrupt is available if ...

  • Page 25

    ... Zilog On the MPU interface, the transmitted data available can be programmed to interrupt the MPU bytes of available data by seeing the appropriate value in the MPU FSCR control register (MPU write only xxECH) bits 6 and 7. A timeout feature exists, Transmit Timeout Timer, Z80182/Z8L182 MIMIC SYNCHRONIZATION CONSIDERATIONS Because of the asynchronous nature of the FIFO’ ...

  • Page 26

    ... Zilog Z80182 MIMIC DOUBLE BUFFERING FOR THE TRANSMITTER The Z80182 Rev DA implements double buffering for the transmitter in 16450 mode and sets the TEMT bit in the LSR Register automatically. When this feature is enabled and character delay emulation is being used (see Figure 9): 1. The PC THRE bit in the LSR Register is set when the THR Register is empty ...

  • Page 27

    ... Zilog PARALLEL PORTS FUNCTIONAL DESCRIPTION The Z80182/Z8L182 has three 8-bit bi-directional Ports. Each bit is individually programmable for input or output (with the exception of PC6 and PC7 which are inputs only). PROGRAMMING The following subsections explain and define the parameters for I/O Address assignments. The three tables in this section describe the mapping of the common registers shared by the MPU and the 16550 MIMIC ...

  • Page 28

    ... Zilog PROGRAMMING (Continued) Table 9. Z80182/Z8L182 ESCC, PIA and MISC Registers Register Name WSG Chip Select Register Z80182 Enhancements Register PC Data Direction Register PC Data Register Interrupt Edge/Pin MUX Control ESCC Chan A Control Register ESCC Chan A Data Register ESCC Chan B Control Register ESCC Chan B Data Register ...

  • Page 29

    ... Zilog Z182 MPU CONTROL REGISTERS Figures 10 through 50 refer to the Z80182/Z8L182 MPU Control registers. For additional information, refer to the Z8S180 Product Specification and Technical Manual. ASCI CHANNELS CONTROL REGISTERS CNTLA0 MPE Bit RE Upon RESET 0 0 R/W R/W R/W DS971820600 Addr 00H MPBR/ ...

  • Page 30

    ... Zilog ASCI CHANNELS CONTROL REGISTERS (Continued) CNTLA1 Bit MPE RE TE Upon RESET R/W R/W R/W R/W 3- Addr 01H CKA1D MPBR/ MOD2 MOD1 MOD0 EFR R/W R/W R/W R/W R/W MODE Selection Start + 7-Bit Data + 1 Stop Start + 7-Bit Data + 2 Stop Start + 7-Bit Data + Parity + 1 Stop ...

  • Page 31

    ... Zilog CNTLB0 Bit MPBT MP Upon Reset Invalid 0 R/W R/W R/W † /CTS - Depending on the condition of /CTS pin Cleared to 0. General Divide Ratio (Divide Ratio = 10) SS (x16) 000 Ø 160 001 Ø 320 010 Ø 640 011 Ø 1280 100 Ø 2560 101 Ø ...

  • Page 32

    ... Zilog ASCI CHANNELS CONTROL REGISTERS (Continued) CNTLB1 /CTS/ Bit MPBT MP Upon Reset Invalid 0 R/W R/W R/W R/W General Divide Ratio (Divide Ratio = 10) SS (x16) 000 Ø 160 001 Ø 320 010 Ø 640 011 Ø 1280 100 Ø 2560 101 Ø ...

  • Page 33

    ... Zilog STAT0 RDRF OVRN Bit 0 Upon Reset R R/W †† /CTS0 Pin STAT1 Bit RDRF OVRN 0 Upon Reset R R/W DS971820600 Addr 04H PE FE RIE /DCD0 TDRE TIE † †† R R/W † /DCD0 - Depending on the condition of /DCD0 Pin. TDRE Figure 13. ASCI Status Register ...

  • Page 34

    ... Zilog ASCI CHANNELS CONTROL REGISTERS (Continued) TDR0 Write Only Addr 06H Transmit Data Figure 15. ASCI Transmit Data Register (Ch. 0) TDR1 Write Only Addr 07H Transmit Data Figure 16. ASCI Transmit Data Register (Ch. 1) TSR0 Read Only Addr 08H Received Data Figure 17. ASCI Receive Data Register (Ch. 0) ...

  • Page 35

    ... Zilog CSI/O REGISTERS CNTR Bit EF EIE Upon Reset 0 R R/W R/W SS2 Baud Rate 000 Ø 001 Ø 010 Ø 011 Ø Figure 22. CSI/O Transmit/Receive Data Register DS971820600 Addr 0AH SS2 SS1 SS0 R/W R/W R/W R/W R/W SS2 100 40 101 ...

  • Page 36

    ... Zilog TIMER DATA REGISTERS TMDR0L Read/Write Addr 0CH Figure 23. Timer 0 Data Register L TMDR1L Read/Write Addr 14H Figure 24. Timer 1 Data Register L TIMER RELOAD REGISTERS RLDR0L Read/Write Addr 0EH Figure 27. Timer 0 Reload Register L RLDR1L Read/Write Addr 16H Figure 28. Timer 1 Reload Register L 3- TMDR0H ...

  • Page 37

    ... Zilog TIMER CONTROL REGISTER TCR Bit TIF1 TIF0 Upon Reset TOC1,0 A15/TOUT 00 Inhibited DS971820600 Addr 10H TIE1 TIE0 TOC1 TOC0 TDE1 TDE0 R/W R/W R/W R/W R/W R/W Toggle 0 1 Figure 31. Timer Control Register PS009801-0301 Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL Timer Down Count Enable 1,0 ...

  • Page 38

    ... Zilog FREE RUNNING COUNTER CPU CONTROL REGISTER DMA REGISTERS Figure 34. DMA 0 Source Address Registers 3- FRC Read Only Addr 18H Figure 32. Free Running Counter CPU Control Register (CCR) Addr 1FH Figure 33. CPU Note: See Figure 49 for full description. SAR0L Read/Write Addr 20H ...

  • Page 39

    ... Zilog DMA REGISTERS DAR0L Read/Write Addr 23H DA7 DA0 DAR0H Read/Write Addr 24H DA15 DA8 DAR0B Read/Write Addr 25H DA19 DA16 - - - - Bits 0-2 (3) are used for DAR0B A19, A18, A17, A16 DMA Transfer Request /DREQ0 (external TDR0 (ASCI0 TDR1 (ASCI1 Not Used Figure 35 ...

  • Page 40

    ... Zilog DMA REGISTERS (Continued) DSTAT Bit DE1 DE0 /DWE1 Upon Reset R/W R/W R/W W DMODE Bit - - DM1 Upon Reset 1 1 R/W R/W DM1, 0 Destination I/O MMOD Mode Cycle Steal Mode 0 Burst Mode 1 3- Addr 30H - /DWE0 DIE1 DIE0 DIME R/W R/W R Figure 40 ...

  • Page 41

    ... Zilog DCNTL Bit MWI1 MWI0 Upon Reset 1 1 R/W R/W R/W * MWI1, 0 No. of Wait States DMSi 1 0 DM1 Note using ROM/RAM Chip Select wait state generators, the Z180 wait state generator should be set to 0. DS971820600 Addr 32H IWI1 IWI0 DMS1 DMS0 DIM1 ...

  • Page 42

    ... Zilog MMU REGISTERS CBR Bit CB7 CB6 Upon Reset 0 0 R/W R/W R/W BBR Bit BB6 BB7 Upon Reset 0 0 R/W R/W R/W CBAR Bit CA3 CA2 Upon Reset 1 1 R/W R/W R/W Figure 45. MMU Common/Bank Area Register 3- Addr 38H CB5 ...

  • Page 43

    ... Zilog SYSTEM CONTROL REGISTERS IL Bit IL7 IL6 Upon Reset 0 0 R/W R/W R/W ITC Bit TRAP UFO Upon Reset 0 0 R/W R/W R RCR Bit REFE REFW Upon Reset 1 1 R/W R/W R/W CYC1, 0 Interval of Refresh Cycle DS971820600 Addr 33H IL5 - - - ...

  • Page 44

    ... Zilog SYSTEM CONTROL REGISTERS (Continued) OMCR M1E /M1TE /IOC Bit Upon Reset R/W W R/W R/W Note: This register should be programmed to 0x0xxxxxb (x = don't care part of Initialization. Figure 49. Operation Mode Control Register ICR Bit IOA7 IOA6 IOSTP Upon Reset R/W R/W R/W R/W ...

  • Page 45

    ... Zilog ADDITIONAL FEATURES ON THE Z182 MPU The following is a detailed description of the enhancements to the Z8S180 from the standard Z80180 in the areas of STANDBY, IDLE, and STANDBY-QUICK RECOVERY modes. Add-On Features There are five different power-down modes. SLEEP and SYSTEM STOP are inherited from the Z80180. In SLEEP ...

  • Page 46

    ... Zilog STANDBY Mode Exit with BUS REQUEST Optionally, if the BREXT bit (D5 of CPU Control Register) is set to 1, the Z8S180 exits STANDBY mode when the /BUSREQ input is asserted; the crystal oscillator is then restarted. An internal counter automatically provides time for the oscillator to stabilize, before the internal clocking and the system clock output of the Z8S180 are resumed ...

  • Page 47

    ... Zilog When the part is in IDLE mode, the clock oscillator is kept oscillating, but the clock to the rest of the internal circuit, including the CLKOUT, is stopped completely. IDLE mode is exited in a similar way as STANDBY mode, i.e., RESET, BUS REQUEST or EXTERNAL INTERRUPTS, except that ...

  • Page 48

    ... Zilog CPU Control Register Bit 7. Clock Divide Select. Bit 7 of the CCR allows the programmer to set the internal clock to divide the external clock the bit is 0 and divide-by-one if the bit is 1. Upon reset, this bit is set to 0 and the part is in divide-by-two mode ...

  • Page 49

    ... Zilog ™ Z85230 ESCC CONTROL REGISTERS See Figures 52 and 53 for the ESCC Control registers. For additional information, refer to the ESCC Product Specification /Technical Manual. The Z80182/Z8L182 has two ESCC channels. They can be accessed in any page of I/O space since only the lowest eight address lines are decoded for access ...

  • Page 50

    ... Zilog PROGRAMMING THE ESCC The ESCC contains write registers in each channel that are programmed by the system separately to configure the functional uniqueness of the channels. In the ESCC, the data registers are directly addressed by selecting a High on the D//C pin. With all other registers (with the exception of WR0 and RR0), programming the write registers requires two write operations and reading the read registers, both a write and a read operation ...

  • Page 51

    ... Zilog CONTROL REGISTERS Write Register 0 (non-multiplexed bus mode Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Register Null Code Point High Reset Ext/Status Interrupts Send Abort (SDLC Enable Int on Next Rx Character Reset Tx Int Pending ...

  • Page 52

    ... Zilog CONTROL REGISTERS (Continued) Sync7 Sync6 Sync1 Sync0 Sync7 Sync6 Sync3 Sync2 ADR7 ADR6 ADR7 ADR6 Sync7 Sync6 Sync5 Sync4 Sync15 Sync14 Sync11 Sync10 0 1 Figure 52. Write Register Bit Functions (Continued) 3- Write Register CRC Enable RTS /SDLC/CRC-16 Tx Enable Send Break Bits(Or Less)/Character ...

  • Page 53

    ... Zilog WR 7' Prime Auto Tx Flag Auto EOM Reset Auto RTS Deactivation Rx FIFO Int Level DTR/REQ Timing Mode Tx FIFO Int Level Extended Read Enable 32-bit CRC Enable Write Register VIS NV DLC MIE Status High//Status Low Software INTACK Enable Reset 0 1 Not used ...

  • Page 54

    ... Zilog CONTROL REGISTERS (Continued) Write Register TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 Write Register TC8 TC9 TC10 TC11 TC12 TC13 TC14 TC15 Figure 52. Write Register Bit Functions (Continued) 3- Write Register Lower Byte of Time Constant Null Command Enter Search Mode ...

  • Page 55

    ... Zilog Read Register Character Available Zero Count Tx Buffer Empty DCD Sync/Hunt CTS Tx Underrun/EOM Break/Abort Read Register All Sent Residue Code 2 Residue Code 1 Residue Code 0 Parity Error Rx Overrun Error CRC/Framing Error End of Frame (SDLC) Read Register Figure 52. Write Register Bit Functions (Continued) ...

  • Page 56

    ... Zilog CONTROL REGISTERS (Continued) Read Register Loop 0 0 Loop Sending 0 Two Clocks Missing One Clock Missing Read Register TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 3- Read Register Read Register Lower Byte of Time Constant Figure 53. Read Register Bit Functions PS009801-0301 Z80182/Z8L182 ...

  • Page 57

    ... Zilog Z182 MISCELLANEOUS CONTROL AND INTERFACE REGISTERS Figures 54 through 65 describe miscellaneous registers that control the Z182 configuration, RAM/ROM chip select, interrupt and various status and timers Daisy Chain 0=ESCC 1=16550 MIMIC> ESCC ESCC/MIMIC 0=ESCC Channel B 1=16550 MIMIC Interface Tri-Muxed Pins 0=Z80180 ...

  • Page 58

    ... Zilog Z182 MISCELLANEOUS CONTROL AND INTERFACE REGISTERS Table 12b. Data Bus Direction (Z182 Bus Master) Interrupt Acknowledge Transaction Intack For On-Chip Peripheral (IEI=1) Z80182/Z8L182 Data Bus (DD =0) OUT Z80182/Z8L182 Data Bus Out (DD =1) OUT Table 13a. Data Bus Direction (Z80182/Z8L182 is not Bus Master) ...

  • Page 59

    ... Zilog Z182 MISCELLANEOUS CONTROL AND INTERFACE REGISTERS Bit 3 Disable ROMs If this bit disables the ROMCS pin addresses below the ROM boundary set by the ROMBR register will cause the ROMCS pin to go Low. Bit 2 Tri-Muxed Pins Select The Z80182/Z8L182 has three pins that are triple multiplexed and controlled by bit 2 and bit 1 ...

  • Page 60

    ... Zilog /RAMCS AND /ROMCS REGISTERS (Continued) RAMUBR, RAMLBR RAM Upper Boundary Range, RAM Lower Boundary Range These two registers specify the address range for the /RAMCS signal. When accessed memory addresses are less than or equal to the value programmed in the RAMUBR and greater than or equal to the value programmed in the RAMLBR, /RAMCS is asserted ...

  • Page 61

    ... Zilog INTERRUPT EDGE/PIN MUX REGISTER Bits 7-6. These bits control the interrupt capture logic for the external /INT2 PIN. When programmed as ‘0X’, the /INT2 pin performs as the normal level detecting interrupt pin. When programmed as 10 the negative edge detection is enabled. Any falling edge latches an active Low on the internal /INT2 of the Z180 ...

  • Page 62

    ... Zilog INTERRUPT EDGE/PIN MUX REGISTER (Continued) Bit 0. Programming this bit to 1 selects a 16 cycle wait delay on recovery from HALT. Halt Recovery is disabled if bit 5 of the enhancement register is set selects no wait delay on Halt recovery. If Halt Recovery is selected, the following pins assume the ...

  • Page 63

    ... Zilog 16550 MIMIC INTERFACE REGISTERS MIMIC Master Control Register (MMC) The 16550 MIMIC interface is controlled by the MMC register. Setting it allows for different modes of operation such as using the 8-bit counters, DMA accesses, and which IRQ structure is used with the PC/XT/AT VIS Vector Include Status ...

  • Page 64

    ... Zilog IUS/IP Register The IUS/IP Register is used by the Z180 the source of the interrupt. This register will have the appropriate bit set when an interrupt occurs Interrupt Pending 6 THR Write 5 TTO Transmitter Timeout 4 RBR Read 3 MCR Write 2 LCR Write 1 DLL Write 1 DLM Write ...

  • Page 65

    ... Zilog Interrupt Enable Register The IE Register allows each of the 16550/8250 interrupts ™ to the Z180 MPU to be masked off individually or globally Interrupt Enable 6 Enable THR IRQ 5 Enable TTO IRQ 4 RBR IRQ 3 Enable LCR IRQ 2 Enable MCR IRQ 1 Enable DLL/DLM IRQ 0 Enable FCR IRQ MIE Figure 62 ...

  • Page 66

    ... Zilog Interrupt Vector Register (Continued) Table 16. Interrupt Status Bits Bits Interrupt Request 000 NO IRQ 001 FCR or Tx OVRN IRQ 010 DLL/DLM IRQ 011 LCR IRQ* 100 MCR IRQ* 101 RBR IRQ 110 TTO IRQ 111 THR IRQ Note: * The order of LCR and MCR does not follow that of the IE Register. ...

  • Page 67

    ... Zilog Bit 0 16450 MIMIC Mode Enable (Reset value=0) This bit = 1 will force the mimic into 16450 mode. Bit 0 in the FCR reg is forced to zero as well as the mimic internal FIFO enable. When used, this bit should be programmed at MIMIC initialization and not modified afterwards ...

  • Page 68

    ... Zilog Transmit And Receive Timers (Continued) When a write from the PC/XT/AT is made to the Transmit Holding Register, an interrupt to the Z180 MPU is generated. The Z180 MPU then reads the data in the Transmit Holding Register. Upon this read, if the Transmitter timer is enabled, the time constant from the Transmitter Time Constant Register is loaded into the Transmitter timer and enables the count ...

  • Page 69

    ... Zilog 16550 MIMIC REGISTERS The Z80182/Z8L182 contains the following set of registers for interfacing with the PC/XT/AT. – Receive Buffer Register – Transmit Holding Register – Interrupt Enable Register – Interrupt Identification Register – FIFO Control Register – Line Control Register – Modem Control Register – ...

  • Page 70

    ... Zilog 16550 MIMIC REGISTERS (Continued) FIFO Control Register Bit 6 and Bit 7 RCVR trigger LSB and MSB bits This 2-bit field determines the number of available bytes in the receiver FIFO before an interrupt to the PC occurs (see Table 18). Bit 4 and Bit 5 Reserved for future use (PC side). Note: From the MPU side, bit 4 and bit 5 flags two sources of interrupts. Bit FIFO interrupt indicating that the FCR had changed ...

  • Page 71

    ... Zilog Although this bit is disabled by default advised that this bit is enabled to prevent interrupt conflict between MIMIC and ESCC interrupts Figure 73. Interrupt Identification Register (PC Read Only, Address 02H) (Z180 MPU no access) Interrupt Identification Register Bit 7 and Bit 6 FIFO’s Enabled These bits will read 1 if the FIFO mode is enabled on the MIMIC ...

  • Page 72

    ... Zilog 16550 MIMIC REGISTERS (Continued) Line Status Register Bit 7 Error in RCVR FIFO In 16450 mode, this bit will read logic 0. In 16550 mode this bit is set if at least one data byte is available in the FIFO with one of its associated error bits set. This bit will clear when there are no more errors (or break detects) in the FIFO ...

  • Page 73

    ... Zilog Figure 76. Line Control Register (PC Read/Write, Address 03H) (Z180 MPU Read Only, Address xxF3H) Line Control Register Bit 7 Divisor Latch Access Bit (DALB) This bit allow access to the divisor latch by the PC/XT/AT. If this bit is set to 1, access to the Transmitter, Receiver and Interrupt Enable Registers is disabled ...

  • Page 74

    ... Zilog 16550 MIMIC REGISTERS (Continued) Modem Status Register Bit 7 Data Carrier Detect This bit must be written by the Z180 MPU. Bit 6 Ring Indicator This bit must be written by the Z180 MPU. Bit 5 Data Set Ready This bit must be written by the Z180 MPU. Bit 4 Clear to Send ...

  • Page 75

    ... Zilog Z80182 ENHANCEMENTS REGISTER Bit <7-6> Reserved Bit 5 Force Z180 Halt Mode If this bit is set disables the 16 cycle halt recovery and halt control over the busses and pins. This bit is used to allow DMA and Refresh Access to take place during halt (like Z180). This bit is set reset. ...

  • Page 76

    ... Zilog PARALLEL PORTS REGISTERS The Z80182/Z8L182 has three 8-bit bi-directional Ports. Each bit is individually programmable for input or output. The Ports consist of two registers the Port Direction Control Register and the Port Data Register. The Port and direction register can be accessed in any page of I/O space since only the lowest eight address lines are decoded ...

  • Page 77

    ... Zilog The data direction register determines which are inputs and outputs in the PC Data Register. When a bit is set to 1 the corresponding bit in the PC Data Register is an input. If the bit is 0, then the corresponding bit is an output Data Register /INT2, /INT1 Read Ext Data ...

  • Page 78

    ... Zilog Z80182/Z8L182 MIMIC DMA CONSIDERATIONS For the PC Interface, the 16550 device has two modes of operation that need to be supported by the MIMIC. In single transfer mode, the DMA request line for the receiver goes active whenever there is at least one character in the RCVR FIFO. For the transmitter, the DMA request line is active on an empty XMIT FIFO and inactive on non-empty ...

  • Page 79

    ... Zilog EMULATION MODES (Continued) Table 21. Emulation Mode 1 Normal Signal Mode 0 PHI Output /M1 Output /MREQ,/MRD Output /IORQ Output /RD Output /WR Output /RFSH Output /HALT Output ST Output E Output /BUSACK Output /WAIT Input A19,A18/T Output OUT A17-A0 Output D7-D0 Input/Output TxA0 Output /RTS0 Output ...

  • Page 80

    ... Zilog ABSOLUTE MAXIMUM RATINGS Voltage on V with respect to V ........... –0.3V to +7. Voltages on all inputs with respect to V ........................... –0. Operating Ambient Temperature ................... 0 to +70 C Storage Temperature ............................ – +150 C STANDARD TEST CONDITIONS The DC Characteristics and capacitance sections below apply for the following standard test conditions, unless otherwise noted ...

  • Page 81

    ... Zilog DC CHARACTERISTICS Z80182/Z8L182 ( 10 0V, over specified temperature range unless otherwise notes Symbol Parameter V Input H Voltage IH1 /RESET, EXTAL, NMI V Input H Voltage IH2 Except /RESET, EXTAL, NMI V Input L Voltage IL1 /RESET, EXTAL, NMI V Input L Voltage IL2 Except /RESET, EXTAL, NMI V Output H Voltage ...

  • Page 82

    ... Zilog DC CHARACTERISTICS Z80182/Z8L182 (V = 3.3V 10 0V, over specified temperature range unless otherwise notes Symbol Parameter V Input H Voltage IH1 /RESET, EXTAL, NMI V Input H Voltage IH2 Except /RESET, EXTAL, NMI V Input L Voltage IL1 /RESET, EXTAL, NMI V Input L Voltage IL2 Except /RESET, EXTAL, NMI V Output H Voltage ...

  • Page 83

    ... Zilog TIMING DIAGRAMS Z180 MPU Timing Opcode Fetch Cycle ø Address 19 /WAIT 7 /MREQ 8 /IORQ /RD 9 /WR / Data IN Data OUT 63 62 /RESET 68 67 (Opcode Fetch Cycle, Memory Read/Write Cycle DS971820600 I/O Write Cycle † I/O Read Cycle † Figure 90. CPU Timing I/O Read/Write Cycle) ...

  • Page 84

    ... Zilog TIMING DIAGRAMS (Continued) Ø /INTI 33 /NMI /INTSCC [4] /M1 [1] /IORQ [1] /Data IN [1] /MREQ [2] /RFSH [ /BUSREQ /BUSACK Address Data /MREQ, /RD, /WR, /IORQ /HALT Notes: [1] During /INT0 acknowledge cycle [2] During refresh cycle (/INT0 Acknowledge Cycle, Refresh Cycle, BUS RELEASE Mode HALT Mode, SLEEP Mode, SYSTEM STOP Mode) ...

  • Page 85

    ... Zilog I/O Read Cycle Address 28 /IROQ 9 /RD /WR Ø /DREQi (At level sense) /DREQi (At edge sence) /TENDi ST DMA Control Signals 1] tDRQS and tDRQH are specified for the rising edge of clock followed by T3. [ [2] tDRQS and tDRQH are specified for the rising edge of clock. [3] DMA cycle starts. ...

  • Page 86

    ... Zilog TIMING DIAGRAMS (Continued) T1 Ø D7-D0 Ø BUS RELEASE Mode E SLEEP Mode SYSTEM STOP Mode 3- Figure 94. E Clock Timing (Memory Read/Write Cycle I/O Read/Write Cycle) 49 Figure 95. E Clock Timing PS009801-0301 Z80182/Z8L182 ILOG NTELLIGENT DS971820600 ERIPHERAL ...

  • Page 87

    ... Zilog T2 Ø E (Example: I/O Read - Opcode Fetch) E (I/O Write) Ø A18/TOUT DS971820600 Figure 96. E Clock Timing (Minimum timing example of PWEL and PWEH) Timer Data Reg = 0000H 55 Figure 97. Timer Output Timing PS009801-0301 Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL 3-87 ...

  • Page 88

    ... Zilog TIMING DIAGRAMS (Continued) SLP Instruction Fetch T3 T1 Ø /INTi /NMI A18-A0 /MREQ, /M1 /RD /HALT 3- Figure 98. SLEEP Execution Cycle PS009801-0301 Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL Next Opcode Fetch DS971820600 ...

  • Page 89

    ... Zilog CSI/O Clock Transmit Data (Internal Clock) Transmit Data (External Clock) Receive Data (Internal Clock) Receive Data (External Clock) /MREQ /RAMCS /ROMCS /IORQ /IOCS DS971820600 tcyc 58 59 11.5 tcyc 16.5 tcyc 60 61 Figure 99. CSI/O Receive/Transmit Timing Figure 100 /ROMCS and /RAMCS Timing ...

  • Page 90

    ... Zilog TIMING DIAGRAMS (Continued Address /MREQ /RD /WR /MRD 9 7 /MWR 22 65 EXTAL VIH1 VIH1 VIL1 Figure 102. External Clock Rise Time and Fall Time 3- Address Valid Figure 101. /MWR and /MRD Timing 66 70 VIL1 Figure 103. Input Rise and Fall Time ...

  • Page 91

    ... Zilog Z8S180 AC CHARACTERISTICS No. Sym Parameter 1 tcyc Clock Cycle Time 2 tCHW Clock Pulse Width (High) 3 tCLW Clock Pulse Width (Low) 4 tcf Clock Fall Time 5 tcr Clock Rise Time 6 tAD Address Valid from Clock Rise 7 tAS Address Valid to /MREQ, /IORQ, /MRD Fall 8 tMED1 ...

  • Page 92

    ... Zilog Z8S180 AC CHARACTERISTICS (Continued) No. Sym Parameter 41 tRFD1 Clock Rise to /RFSH Fall Delay 42 tRFD2 Clock Rise to /RFSH Rise Delay 43 tHAD1 Clock Rise to /HALT Fall Delay 44 tHAD2 Clock Rise to /HALT Rise Delay 45 tDRQS /DREQi Setup Time to Clock Rise 46 tDRQH /DREQi Hold Time from Clock Rise ...

  • Page 93

    ... Zilog ESCC Timing Ø /WR /RD /W//REQ Wait /W//REQ Request /DTR//REQ Request /INT No. Symbol Parameter 1 TdWR(W) /WR Fall to Wait Valid Delay 2 TdRD(W) /RD Fall to Wait Valid Delay 3 TdWRf(REQ) /WR Fall to /W//REQ Not Valid Delay 4 TdRDf(REQ) /RD Fall to /W//REQ Not Valid Delay 5 TdRdr(REQ) /RD Rise to /DTR//REQ ...

  • Page 94

    ... Zilog AC CHARACTERISTICS (Continued) Z85230 General Timing Diagram PCLK /W//REQ Request /W//REQ Wait /RTxC, /TRxC Receive 4 RxD 8 /SYNC External /TRxC, /RTxC Transmit TxD 13 /TRxC Output /RTxC /TRxC /CTS, /DCD /SYNC Input 3- Figure 105. General Timing Diagram PS009801-0301 Z80182/Z8L182 Z I ILOG NTELLIGENT DS971820600 ...

  • Page 95

    ... Zilog No. Symbol 1 TdPC(REQ) 2 TdPC(W) 3 TsRxC(PC) 4 TsRxD(RxCr) 5 ThRxD(RxCr) 6 TsRxD(RxCf) 7 ThRxD(RxCf) 8 TsSY(RxC) 9 ThSY(RXC) 10 TsTxC(PC) 11 TdTxCf(TXD) 12 TdTxCr(TXD) 13 TdTxD(TRX) 14 TwRTxh 15 TwRTxI 16a TcRTx 16b TxRx(DPLL) 17 TcRTxx 18 TwTRxh 19 TwTRxl 20 TcTRx 21 TwExT 22 TwSY Notes: These AC parameter values are preliminary and subject to change without notice. [1] RxC is /RTxC or /TRxC, whichever is supplying the receive clock. ...

  • Page 96

    ... Zilog AC CHARACTERISTICS (Continued) Z85230 System Timing Diagram /RTxC, /TRxC Receive /W/REQ Request /W/REQ Wait /SYNC Output /INT /RTxC, /TRxC Transmit /W//REQ Request /W//REQ Wait /DTR//REQ Request /INT /CTS, /DCD /SYNC Input /INT 3- Figure 106. Z85230 System Timing PS009801-0301 Z80182/Z8L182 ILOG ...

  • Page 97

    ... Zilog No. Symbol 1 TdRxC(REQ) 2 TdRxC(W) 3 TdRxC(SY) 4 TdRxC(INT) 5 TdTxC(REQ) 6 TdTxC(W) 7 TdTxC(DRQ) 8 TdTxC(INT) 9 TdSY(INT) 10 TdExT(INT) Notes: These AC parameters values are preliminary and subject to change without notice. [1] Open-drain output, measured with open-drain test load. [2] /RxC is /RTxC or /TRxC, whichever is supplying the receive clock. [3] /TxC is /TRxC or /RTxC, whichever is supplying the transmit clock. ...

  • Page 98

    ... Zilog General-Purpose I/O Port Timing This figure shows the timing for the Ports A, B and C. Parameters referred to in this figure appear in Tables D and E. I/O Port Timing (Output Port Data Dir. Reg. Addr. (Input) A0-A7 F1 /IORQ (In) 'OO'H (Change Port To Output) D0- /WR E3 Port I/O Port Timing (Input) Port Data Dir ...

  • Page 99

    ... Zilog Read Write External Bus Master Timing Address A7-A0 /IORQ /RD Data /WR Data Figure 108. Read/Write External Bus Master Timing DS971820600 Data In PS009801-0301 Z80182/Z8L182 Z I ILOG NTELLIGENT F5 F7 Data Out ERIPHERAL 3-99 ...

  • Page 100

    ... Zilog ESCC External Bus Master Timing Valid ESCC Addr * IORQ /RD or /WR DTR/REQ Request Figure 109. ESCC External Bus Master Timing Table G. External Bus Master Interface Timing (SCC Related Timing) No. Symbol Parameter 1 TrC Valid Access Recovery Time 2 TdRDr(REQ) /RD Rise to /DTR//REQ Not Valid Delay Notes: These AC parameter values are preliminary and are subject to change without notice ...

  • Page 101

    ... Zilog 16550 MIMIC TIMING Refer to Figures 106 thru 112 for MIMIC AC Timing. HA2, HA1, HA0 /HCS /HRD /HWR No Symbol Parameter 1 tAR /HRD Delay from Address 2 tCSR /HRD Delay from /HCS 3 tAW /HWR Delay from Address 4 tCSW /HWR Delay from /HCS 5 tAh ...

  • Page 102

    ... Zilog 16550 MIMIC TIMING (Continued) HD7-HD0 /HWR Figure 111. Data Setup and Hold, Output Delay, Write Cycle HD7-HD0 /HRD Figure 112. Data Setup and Hold, Output Delay, Read Cycle Table I. Data Setup and Hold, Output Delay, Read Cycle No. Sym Parameter 7 tDs ...

  • Page 103

    ... Zilog No. Sym Parameter 13 tRDD /HRD to Driver Enable/Disable Note: These AC parameter values are preliminary and are subject to change without notice. /WR (MPU) RBR HINTR (Trigger Level) HINTR (Line Status RDR /HRD LSR /HRD RBR DS971820600 /HRD /HDDIS 13 Figure 113. Driver Enable Timing Table J. Driver Enable Timing ...

  • Page 104

    ... Zilog 16550 MIMIC TIMING (Continued) No. Sym Parameter 14 tSINT Delay from Stop to Set Interrupt 15 tRINT Delay from /HRD (RD RBR or RD LSR) to Reset Interrupt Note: These AC parameter values are preliminary and are subject to change without notice. /RD (MPU) TxFIFO HINTR THRE /WR (Host) THR /RD (Host) 11R Figure 115 ...

  • Page 105

    ... Zilog No. Sym Parameter 16 tHR Delay from /WR (WR THR) to Reset Interrupt 17 TSTI Delay from Stop to Interrupt (THRE) 18 TIR Delay from /RD (RD IIR) to Reset Interrupt (THRIE) /HRD RD_RBR /WR (MPU) RCVR FIFO (First Byte that reaches Trigger Level) /HRXRDY /HWR (Host) THR RD (MPU) THR (Last ...

  • Page 106

    ... Zilog 16550 MIMIC TIMING (Continued) Table M. RCVR FIFO Bytes Other Than First No Sym Parameter 19 tRXi Delay from /HRD RBR to /HRxRDY Inactive 20 TWxi Delay from Write to /HTxRDY Inactive 21 tSXa Delay From Start to /HTxRDY Active Note: These AC parameter values are preliminary and are subject to change without notice. ...

  • Page 107

    ... Zilog PACKAGE INFORMATION DS971820600 100-Pin VQFP Package Diagram PS009801-0301 Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL 3-107 ...

  • Page 108

    ... Zilog PACKAGE INFORMATION (Continued) 3-108 100-Pin QFP Package Diagram PS009801-0301 Z80182/Z8L182 ILOG NTELLIGENT ERIPHERAL DS971820600 ...

  • Page 109

    ... ORDERING INFORMATION Z8L182 Z80182 20 MHz 33 MHz Z8L18220ASC Z8018233ASC Z8L18220FSC Z8018233FSC For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired. Preferred Package A = VQFP (Very Small QFP Plastic Quad Flatpack Preferred Temperature +70 C Speeds MHz MHZ Environmental ...