Z8018233ASG Zilog, Z8018233ASG Datasheet - Page 65

• Manufacturer Part Number: Z8018233ASG
• Description: IC 33MHZ STATIC MIMIC 100-LQFP
• Manufacturer: Zilog

Specifications of Z8018233ASG

• Processor Type: Z180
• Features: Smart Peripheral Controller
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Interface Type: UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 7 Master Interrupt Enable (Read/Write)
If bit 7 is 0, all interrupts from the 16550 MIMIC are masked
off. If this bit is 1, then interrupts are enabled individually by
setting the appropriate bit.
Bit 6 Enable THR Interrupt (Read/Write)
If this bit is 1, it enables the Transmit Holding Register
Interrupt.
Bit 5 Enable TTO Interrupt (Read/Write)
If this bit is 1, it enables the Transmitter Timeout Interrupt.
This interrupts the CPU when characters remain in the
FIFO below the trigger level and the FIFO is not read or
written for the length of time in the transmitter timeout
register.
Bit 4 Enable RBR Interrupt (Read/Write)
If this bit is 1, it enables the Receive Buffer Register
Interrupt.
Bit 3 Enable LCR Interrupt (Read/Write)
If this bit is 1, it enables the Line Control Register interrupt.
Bit 2 Enable MCR Interrupt (Read/Write)
If this bit is 1, it enables the Modem Control Register
Interrupt.
Bit 1 Enable DLL/DLM Interrupt (Read/Write)
If this bit is 1, it enables the Divisor Latch Least and Most
Significant Byte interrupts.
Bit 0 Enable FCR Interrupt (Read/Write)
If this bit is 1 , then interrupts are enabled for a PC write to
the FIFO control register (FCR) or for occurrence of Tx
Overrun.
DS971820600
Interrupt Enable Register
The IE Register allows each of the 16550/8250 interrupts
to the Z180
Zilog
D7 D6
0
0
D5 D4 D3 D2 D1 D0
0
™
MPU to be masked off individually or globally.
0
(Z180 MPU, Address xxFDH)
0
Figure 62. IE Register
0
0
0
MIE
Interrupt Enable
6 Enable THR IRQ
5 Enable TTO IRQ
4 RBR IRQ
3 Enable LCR IRQ
2 Enable MCR IRQ
1 Enable DLL/DLM IRQ
0 Enable FCR IRQ
P R E L I M I N A R Y
PS009801-0301
Priority of interrupts are in this order:
Interrupt Vector Register
The Interrupt Vector Register contains either the opcode
(Z180 Interrupt Mode 0) or the modified vector used as the
lower address for a Z180 interrupt service routine (Z180
Interrupt Mode 2), depending upon the VIS bit in the MMC
Register (MIMIC Master Control Register). If the VIS bit is
0, then Z180 Mode 0 interrupt is selected; if VIS is 1, then
Z180 Mode 2 is selected. Note that in Z180 Interrupt Mode
0, the data input to the MPU during the interrupt
acknowledge cycle is an instruction opcode; in Z180
Interrupt Mode 2, this data (modified depending on the
source of the interrupt) becomes part of an address from
which to get the starting address of the interrupt service
routine.
Bits 7-4 Upper Nibble IVEC (Read/Write)
These four bits generate either an opcode for Z180 Interrupt
Mode 0, or the upper four bits of the interrupt modified
vector used as an 8-bit address to support the Z180
Interrupt Mode 2. These bits are read/write and always
read back what was last written to them.
Bits 3-1 Interrupt Modified Vector/Opcode
(Read/Write Table 16)
These three bits are the Interrupt Status bits when VIS in
the MMC register is 1 (Z180 Interrupt Mode 2). If VIS bit is
0, then this field contains bit 3-bit 1 of the opcode. If the VIS
bit is 0, then these bits contain what was last written to
them.
(Highest) 6
(Lowest)
D7 D6
0
0
D5 D4 D3 D2 D1 D0
0
(Z180 MPU, Address xxFCH)
5
4
3
2
1
1
0
Figure 63. IVEC Register
0
THR IRQ
TTO IRQ
RBR IRQ
MCR IRQ
LCR IRQ
DLL IRQ
DLM IRQ
FCR or Tx OVERRUN IRQ
0
0
0
0
Z
ILOG
0/Opcode
Upper Nibble IVEC
Status/Opcode
I
NTELLIGENT
Z80182/Z8L182
P
ERIPHERAL
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