Z8018233ASG Zilog, Z8018233ASG Datasheet - Page 70

• Manufacturer Part Number: Z8018233ASG
• Description: IC 33MHZ STATIC MIMIC 100-LQFP
• Manufacturer: Zilog

Specifications of Z8018233ASG

• Processor Type: Z180
• Features: Smart Peripheral Controller
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Interface Type: UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Zilog
16550 MIMIC REGISTERS (Continued)
FIFO Control Register
Bit 6 and Bit 7 RCVR trigger LSB and MSB bits
This 2-bit field determines the number of available bytes in
the receiver FIFO before an interrupt to the PC occurs (see
Table 18).
Bit 4 and Bit 5
Reserved for future use (PC side). Note: From the MPU
side, bit 4 and bit 5 flags two sources of interrupts. Bit 5 is
a FIFO interrupt indicating that the FCR had changed; bit
4 is a Tx overrun interrupt, indicating transmit overrun. A
read of the FCR from the MCU side will clear a previously
set bit 4 or bit 5.
Bit 3 DMA mode select
Setting this bit to 1 will cause the MIMIC DMA mode to
change from mode 0 to mode 1 (if bit 0 is 1, FIFO mode is
enabled). This affects the DMA mode of the FIFO. A 1 in this
bit enables multi-byte DMA).
Bit 2 XMIT FIFO Reset
Setting this bit to 1 will cause the transmitter FIFO pointer
logic to be reset; any data in the FIFO will be lost. This bit
is self clearing; however a shadow bit exists that is cleared
only when read by the Z180 MPU, allowing the MPU to
monitor a FIFO reset by the PC.
Bit 1 RCVR FIFO Reset
Setting this bit to 1 will cause the receiver FIFO pointer
logic to be reset; any data in the FIFO will be lost. This bit
is self clearing, however a shadow bit exists that is cleared
only when read by the Z180 MPU, allowing the MPU to
monitor a FIFO reset by the PC.
Bit 0 FIFO Enable
The PC writes this bit to logic 1 to put the 16550 MIMIC into
FIFO mode. This bit must be 1 when writing to the other bits
in this register or they will not be programmed. When this
bit changes state, any data in the FIFO’s or transmitter
holding and Receive Buffer Registers is lost and any
pending interrupts are cleared. This feature can be forced
in a disabled state by the MPU.
3-70
P R E L I M I N A R Y
PS009801-0301
Bit 7-2 Reserved. Program to zero.
Bit 1 RCVR Overrun Modification
The actual 16450/16550 device allows the last position in
FIFO to be overwritten by DCE during receiver overrun
condition. When this bit is enabled (programmed to 1) the
last position in FIFO can be overwritten by Z180 during
receiver overrun. This feature is disabled by default. When
this modification is not enabled, the MIMIC will ignore any
write to RBR during an overrun condition.
Bit 0 Fast MIMIC-ESCC Interrupt Resolution
When enabling this modification, the internal MIMIC IEO
signal into the ESCC IEI input is forced Low when the
MIMIC Interrupt line becomes active. This is required to
prevent the ESCC from putting it's vector on the databus
during an INTACK cycle (given that the MIMIC is
programmed to have higher interrupt priority).
When disabled, the internal MIMIC IEO becomes
deasserted only after an interrupt acknowledge cycle. In
this case, it is possible for the ESCC to force it's interrupt
vector onto the data bus even when the MIMIC has a
pending interrupt and is higher in priority.
D7 D6 D5 D4 D3 D2 D1 D0
0
b7
0
0
1
1
Figure 72. MIMIC Modification Register
0
(Z180 MPU Write only, Address xxE9h)
Table 18. Receive Trigger Level
0
b6
0
1
0
1
0
0
Trigger Level, Number of Bytes
0
0
0
14
Z
1
4
8
Fast Interrupt Resolution
16550/450 RCVR Overrun
ILOG
I
NTELLIGENT
DS971820600
Z80182/Z8L182
P
ERIPHERAL