Z8018233ASG Zilog, Z8018233ASG Datasheet - Page 91

• Manufacturer Part Number: Z8018233ASG
• Description: IC 33MHZ STATIC MIMIC 100-LQFP
• Manufacturer: Zilog

Specifications of Z8018233ASG

• Processor Type: Z180
• Features: Smart Peripheral Controller
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Interface Type: UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z8S180 AC CHARACTERISTICS
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
26a
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DS971820600
Zilog
Sym
tcyc
tCHW
tCLW
tcf
tcr
tAD
tAS
tMED1
tRDD1
tM1D1
tAH
tMED2
tRDD2
tM1D2
tDRS
tDRH
tSTD1
tSTD2
tWS
tWH
tWDZ
tWRD1
tWDD
tWDS
tWRD2
tWRP
tWDH
tIOD1
tIOD2
tIOD3
tINTS
tINTH
tNMIW
tBRS
tBRH
tBAD1
tBAD2
tBZD
tMEWH
tMEWL
Address Hold time (/MREQ, /IORQ, /RD, /WR/MRD)
Clock Fall to /RD, /MRD Rise Delay
Data Read Hold Time
/WAIT Setup Time to Clock Fall
Clock Rise to Data Float Delay
Clock Rise to /WR,/MWR Fall Delay
Clock Fall to /WR Rise
/WR Pulse Width (Memory Write Cycles)
/INT Setup Time to Clock Fall
/BUSREQ Hold Time from Clock Fall
/MREQ Pulse Width (Low)
Parameter
Clock Cycle Time
Clock Pulse Width (High)
Clock Pulse Width (Low)
Clock Fall Time
Clock Rise Time
Address Valid from Clock Rise
Address Valid to /MREQ, /IORQ, /MRD Fall
Clock Fall to /MREQ Fall Delay
Clock Fall to /RD, /MRD (/IOC=1)
Clock Rise to /RD, /MRD Fall (/IOC=0)
Clock Rise to /M1 Fall delay
Clock Fall to /MREQ Rise Delay
Clock Rise to /M1 Rise Delay
Data Read Setup Time
Clock Edge to ST Fall
Clock Edge to ST Rise
/WAIT Hold Time from Clock Fall
Clock Fall to Write Data Delay
Write Data Setup Time to /WR,/MWR Fall
/WR Pulse Width (I/O Write Cycles)
Write Data Hold Time from /WR Rise
Clock Fall to /IORQ Fall Delay (/IOC=1)
Clock Rise to /IORQ Fall Delay (/IOC=0)
Clock Fall /IOQR Rise Delay
/M1 Fall to /IORQ Fall Delay
/INT Hold Time from Clock Fall
/NMI Pulse Width
/BUSREQ Setup Time to Clock Fall
Clock Rise to /BUSACK Fall Delay
Clock Fall to /BUSACK Rise Delay
Clock Rise to Bus Floating Delay Time
/MREQ Pulse Width (High)
Table A. Z8L180 and Z8S180 Timings
PS009801-0301
P R E L I M I N A R Y
Min
50
15
15
5
5
15
0
15
10
10
75
130
10
100
20
10
35
10
10
35
35
Z8L180
20 MHz
Max
2000
10
10
15
15
25
35
35
25
25
40
30
30
35
25
25
25
25
25
25
25
25
40
Min
30
10
10
5
5
15
0
10
5
10
45
70
5
80
15
10
25
10
10
25
25
Z8S180
33 MHz
Max
2000
5
5
15
10
15
15
15
15
15
15
15
15
20
15
15
15
15
15
15
15
15
30
Z
ILOG
I
NTELLIGENT
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Z80182/Z8L182
P
Note
ERIPHERAL
[1]
[1]
[1]
[1]
[1]
[2]
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