Z8018233ASG Zilog, Z8018233ASG Datasheet - Page 92

• Manufacturer Part Number: Z8018233ASG
• Description: IC 33MHZ STATIC MIMIC 100-LQFP
• Manufacturer: Zilog

Specifications of Z8018233ASG

• Processor Type: Z180
• Features: Smart Peripheral Controller
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Interface Type: UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Zilog
Z8S180 AC CHARACTERISTICS (Continued)
No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Notes:
These AC parameters values are preliminary and subject to change without notice.
[1] All specifications reflect 100% output drive (disabled slew rate limiting feature).
[2] Specification 1 through 5 refer to PHI clock output.
[3] Exceeds characterization (data propagation delay needs to be analyzed).
3-92
Sym
tRFD1
tRFD2
tHAD1
tHAD2
tDRQS
tDRQH
tTED1
tTED2
tED1
tED2
PWEH
PWEL
tEr
tEf
tTOD
tSTDI
tSTDE
tSRSI
tSRHI
tSRSE
tSRHE
tRES
tREH
tOSC
tEXr
tEXf
tRr
tRf
tIr
tIf
TdCS
TdIOCS
Clock Rise to /HALT Fall Delay
Clock Rise to /HALT Rise Delay
/DREQi Setup Time to Clock Rise
Clock Fall to /TENDi Fall Delay
Clock Fall to /TENDi Rise Delay
Clock Fall to Timer Output Delay
CSI/O Tx Data Delay Time
CSI/O Rx Data Setup Time
Oscillator Stabilization Time
External Clock Rise Time (EXTAL)
External Clock Fall Time (EXTAL)
/RESET Fall Time
/MREQ Valid to /ROMCS, /RAMCS Valid Delay
Parameter
Clock Rise to /RFSH Fall Delay
Clock Rise to /RFSH Rise Delay
/DREQi Hold Time from Clock Rise
Clock Rise to E Rise Delay
Clock Edge to E Fall Delay
E Pulse Width (High)
E Pulse Width (Low)
Enable Rise Time
Enable Fall Time
(Internal Clock Operation)
CSI/O Tx Data Delay Time
(External Clock Operation)
(Internal Clock Operation)
CSI/O Rx Data Hold Time
(Internal Clock Operation)
CSI/O Rx Data Setup Time
(External Clock Operation)
CSI/O Rx Data Hold Time
(External Clock Operation)
/RESET Setup time to Clock Fall
/RESET Hold time from Clock Fall
/RESET Rise Time
Input Rise Time (Except EXTAL, /RESET)
Input Fall Time (Except EXTAL, /RESET)
/IORQ Valid to /IOCS Valid Delay
PS009801-0301
P R E L I M I N A R Y
Min
20
20
25
50
40
25
Z8L180
20 MHz
Max
20
20
15
15
25
25
30
30
10
10
75
75
7.5 tcyc+100
1
1
1
1
20
10
10
50
50
50
50
15
15
Min
15
15
20
40
1
1
1
1
25
15
Z8S180
33 MHz
Max
15
15
15
15
15
15
15
15
10
10
50
60
7.5 tcyc+100 ns
20
5
5
50
50
50
50
10
10
Z
ILOG
I
NTELLIGENT
Unit
DS971820600
tcyc
tcyc
tcyc
tcyc
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Z80182/Z8L182
P
Note
ERIPHERAL
[2]
[2]
[2]
[2]