MC68EC000EI10 Freescale Semiconductor, MC68EC000EI10 Datasheet
MC68EC000EI10
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... Freescale Semiconductor, Inc. Communications and Advanced Consumer Technologies Group Addendum to M68000 User Manual August 7, 1997 This addendum to the M68000UM/AD User’s Manual , Revision 8, provides corrections to the original text as well as additional information. This document and other information on this product is maintained on the World Wide Web at http://www ...
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... Freescale Semiconductor, Inc. The primary features of the MC68SEC000 embedded processor include the following: • Direct Replacement for the MC68EC000 — Pin-for-pin compatibility with the MC68EC000 in the plastic QFP and TQFP packages — Vast selection of existing third-party development tools for the MC68EC000 support the MC68SEC000 — ...
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... Freescale Semiconductor, Inc. 1.3 MC68SEC000 The MC68SEC000 is a cost-effective static embedded processor engineered for low-power applications. In addition to providing the substantial cost and performance benefits of the MC68EC000, the low-power mode of the MC68SEC000 provides significant advantages in power consumption and power management. The typical current consumption of the MC68SEC000 is only 0 static standby mode and 15.0mA in normal 3 ...
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... Freescale Semiconductor, Inc. 2.0 SIGNAL DESCRIPTION Change Figure 3-3 on Page 3-2. PROCESSOR STATUS SYSTEM CONTROL Figure 1. Input and Output Signals (MC68EC000 and MC68SEC000) 2.1 Data Bus (D15-D0) In Section 3.2 on page 3-4, replace “The MC68EC000 and MC68HC001 use D7-D0 in 8-bit mode, and D15- D8 are undefined.” ...
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... Freescale Semiconductor, Inc. power consumption to its quiescent value low-power mode described below will be routinely tested as part of the MC68SEC000 test vectors provided by Motorola. To successfully enter the low-power mode, the MC68SEC000 must first be in the supervisor mode. A recommended method for entering the low-power mode is to use the TRAP instruction, which causes the processor to begin exception processing, thus entering the supervisor mode ...
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... Freescale Semiconductor, Inc. 8-bit mode requires two bus cycles to fetch the immediate data of the STOP instruction. After the processor clock is disabled often necessary to disable the clock to other sections of your circuit. This can be done, but be careful that runt clocks and spurious glitches are not presented to the MC68SEC000 ...
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... Freescale Semiconductor, Inc. After the previous steps are completed, the MC68SEC000 will remain in the low-power mode until it recognizes the appropriate interrupt . External logic will also have to poll IPLB2–IPLB0 to detect the proper interrupt. When the correct interrupt level is received, the following steps will bring the processor out of the low-power mode: 1 ...
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... Freescale Semiconductor, Inc. An example trap routine is as follows: TRAP_x MOVE.B #0,$low_power_address STOP #$2000 RTE The first instruction (MOVE.B #0,$low_power_address) writes a byte to the low-power address that will cause the external circuitry to begin the sequence that will stop the processor’s clock. The second instruction (STOP #$2000) loads the SR with the immediate data ...
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... Freescale Semiconductor, Inc. 4.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS Replace Figure 10-2 on page 10-6 with Figure 7. DRIVE TO 2.4 V CLK DRIVE TO 0 2.0 V VALID OUTPUTS(1) CLK OUTPUT n 0.8 V OUTPUTS(2) CLK DRIVE TO 2.4 V INPUTS(3) CLK DRIVE TO 0.5 V INPUTS(4) CLK ALL SIGNALS(5) NOTES: 1. This output timing is applicable to all parameters specified relative to the rising edge of the clock. ...
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... Freescale Semiconductor, Inc. 5.0 MC68SEC000 DC ELECTRICAL SPECIFICATIONS Add the following table to Section 10.13 on page 10-23 5.0 Vdc 5%, 3.3 Vdc 10%,; GND = 0 Vdc CHARACTERISTIC Input High Voltage Input Low Voltage Input Leakage Current BERR, BR, DTACK, CLK, I PL2-IPL0, AVEC Three-State (Off State) Input Current ...
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... Freescale Semiconductor, Inc. 6.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS — CLOCK TIMING (See Figure 2) Add the following table and Figure 8 to Section 10.9 on page 10-9. NUM. CHARACTERISTIC Frequency of Operation 1 Cycle time 2,3 Clock Pulse Width 4,5 Clock Rise and Fall Times Applies to 3.3V and 5V. ...
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... Freescale Semiconductor, Inc. 7.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES Add the following table and Figures 9 and 10 to Section 10.16. Applies to 3.3V and 5V. (GND = see Figures 3 and NUM CHARACTERISTIC 6 Clock Low to Address Valid 6A Clock High to FC Valid 7 Clock High to Address, Data Bus High Impedance (Maximum) ...
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... Freescale Semiconductor, Inc. AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (Continued) NUM CHARACTERISTIC 29 AS, LDS, UDS Negated to Data-In Invalid (Hold Time on Read) 29A AS, LDS, UDS Negated to Data-In High Impedance (Read) 30 AS, LDS, UDS Negated to BERR Negated DTACK Asserted to Data-In Valid (Setup Time on Read) ...
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... Freescale Semiconductor, Inc. S0 CLK FC2–FC0 A23– LDS / UDS 17 R/W DTACK DATA IN BERR / BR (NOTE 2) HALT / RESET ASYNCHRONOUS INPUTS (NOTE 1) NOTES: 1. Setup time for the asynchronous inputs IPL2–IPL0 and AVEC (#47) guarantees their recognition at the next falling edge of the clock need fall at this time only to insure being recognized at the end of the bus cycle. ...
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... Freescale Semiconductor, Inc. S0 CLK FC2–FC0 A23– LDS / UDS R/W DTACK DATA OUT BERR / BR (NOTE 2) HALT / RESET ASYNCHRONOUS INPUTS (NOTE 1) NOTES: 1. Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0 ...
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... Freescale Semiconductor, Inc. 8.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS — BUS ARBITRATION Add the following table and Figure 11 to Section 10.17. (GND = 0 Vdc refer to Figure 13 NUM CHARACTERISTICp 7 Clock High to Address, Data Bus High Impedance (Maximum) 16 Clock High to Control Bus High Impedance 33 Clock High to BG Asserted ...
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... Freescale Semiconductor, Inc. STROBES AND R CLK NOTE: Setup time to the clock (#47) for the asynchronous inputs BERR, BR, DTACK, IPL2-IPL0, and VPA guarantees their recognition at the next falling edge of the clock. CLK LDS/UDS DS R/W FC2–FC0 A23 A19–A0 D15 D7–D0 NOTE: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V. ...
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... Freescale Semiconductor, Inc. CLK VMA R/W FC2-FC0 A23-A0 D15-D0 NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V. This diagram also applies to the 68EC000. Figure 13. Bus Arbitration Timing—Idle Bus Case 18 M68000 USER’S MANUAL ADDENDUM ...
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... Freescale Semiconductor, Inc. CLK VMA R/W FC2-FC0 A23-A0 D15-D0 NOTE: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V. This diagram also applies to the 68EC000. Figure 14. Bus Arbitration Timing - Active Bus Case MOTOROLA M68000 USER’S MANUAL ADDENDUM ...
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... Freescale Semiconductor, Inc. CLK VMA R/W FC2-FC0 A23-A0 D15-D0 NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V. This diagram also applies to the 68EC000. Figure 15. Bus Arbitration - Multiple Bus Request 20 M68000 USER’S MANUAL ADDENDUM ...
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... Freescale Semiconductor, Inc. 9.0 MECHANICAL DATA 9.1 PIN ASSIGNMENTS Add Figure 12 to Section 11.1. The following defines the pin assignment and the package dimensions of the 64 lead QFP (FU package) and 64 lead TQFP (PB package) for the MC68SEC000. Note that it is pin-to-pin compatible with the MC68EC000 ...
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... Freescale Semiconductor, Inc. 10.0 PACKAGE DIMENSIONS - FU SUFFIX This diagram replaces the one on Page 11-16 64 Lead Quad Flat Pack Case 840B- DIM M68000 USER’S MANUAL ADDENDUM For More Information On This Product MILLIMETERS MIN MAX MIN 16.95 17.45 0.667 13.90 14.10 0.547 16 ...
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... Freescale Semiconductor, Inc. 11.0 PACKAGE DIMENSIONS - PB SUFFIX Add the following to Section 11.2. 64 Lead Thin Quad Flat Pack Case 840F- DIM MOTOROLA M68000 USER’S MANUAL ADDENDUM For More Information On This Product MILLIMETERS MIN MAX MIN 12.00 BSC 6.00 BSC 10.00 BSC 5 ...
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... Freescale Semiconductor, Inc. 12.0 PACKAGE/FREQUENCY AVAILABILITY Replaces Section 11.1 The following tables identify the packages and operating frequencies available for the MC68HC000, MC68HC001, MC68EC000, and the MC68SEC000. MC68SEC000 PACKAGE Quad Flat Pack (FU) Thin Quad Flat Pack (PB) MC68HC000 PACKAGE Plastic DIP Plastic Quad Pack (PLCC) ...
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... Freescale Semiconductor, Inc. ORDERING INFORMATION Add the following to Section 11. The following tables contains the ordering information for the MC68SEC000. PACKAGE BODY SIZE LEAD SPACING QFP 14 14.0mm TQFP 10.0mm x 10.0mm PACKAGE BODY SIZE DIP 81.91mm X 20.57mm PLCC 25.57mm X 25.27mm PACKAGE BODY SIZE PLCC 25 ...
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... Freescale Semiconductor, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. " ...