MC68HC000EI16 Freescale Semiconductor, MC68HC000EI16 Datasheet - Page 46

• Manufacturer Part Number: MC68HC000EI16
• Description: IC MPU 32BIT 16MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000EI16

• Processor Type: M680x0 32-Bit
• Speed: 16MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

STATE 12
STATE 13
STATE 14
STATE 15
STATE 16 At the rising edge of S16, the processor asserts L D S or DS. The
STATE 17
STATE 18
STATE 19
4.2 OTHER BUS OPERATIONS
Refer to Section 5 16-Bit Bus Operations for information on the following items:
4-8
• CPU Space Cycle
• Bus Arbitration
• Bus Control
• Bus Errors and Halt Operations
• Reset Operations
• Asynchronous Operations
• Synchronous Operations
— Bus Request
— Bus Grant
— Bus Acknowledgment
The write portion of the cycle starts in S12. The valid function codes on
FC2–FC0, the address bus lines, AS, and R/W remain unaltered.
During S13, no bus signals are altered.
On the rising edge of S14, the processor drives R/W low.
During S15, the data bus is driven out of the high-impedance state as the
data to be written are placed on the bus.
processor waits for DTACK or BERR or VPA, an M6800 peripheral signal.
When VPA is asserted during S16, the cycle becomes a peripheral cycle
(refer to Appendix B M6800 Peripheral Interface). If neither termination
signal is asserted before the falling edge at the close of S16, the processor
inserts wait states (full clock cycles) until either DTACK or BERR is asserted.
During S17, no bus signals are altered.
During S18, no bus signals are altered.
On the falling edge of the clock entering S19, the processor negates AS,
L D S , and DS. As the clock rises at the end of S19, the processor
places the address and data buses in the high-impedance state, and drives
R/W high. The device negates DTACK or BERR at this time.
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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