MC68HC000EI16 Freescale Semiconductor, MC68HC000EI16 Datasheet - Page 75

• Manufacturer Part Number: MC68HC000EI16
• Description: IC MPU 32BIT 16MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000EI16

• Processor Type: M680x0 32-Bit
• Speed: 16MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

A double bus fault occurs during a reset operation when a bus error occurs while the
processor is reading the vector table (before the first instruction is executed). The reset
operation is described in the following paragraph.
5.5 RESET OPERATION
RESET is asserted externally for the initial processor reset. Subsequently, the signal can
be asserted either externally or internally (executing a RESET instruction). For proper
external reset operation, HALT must also be asserted.
When RESET and HALT are driven by an external device, the entire system, including the
processor, is reset. Resetting the processor initializes the internal state. The processor
reads the reset vector table entry (address $00000) and loads the contents into the
supervisor stack pointer (SSP). Next, the processor loads the contents of address $00004
(vector table entry 1) into the program counter. Then the processor initializes the interrupt
level in the status register to a value of seven. In the MC68010, the processor also clears
the vector base register to $00000. No other register is affected by the reset sequence.
Figure 5-30 shows the timing of the reset operation.
The RESET instruction causes the processor to assert RESET for 124 clock periods to
reset the external devices of the system. The internal state of the processor is not
affected. Neither the status register nor any of the internal registers is affected by an
internal reset operation. All external devices in the system should be reset at the
completion of the RESET instruction.
For the initial reset, RESET and HALT must be asserted for at least 100 ms. For a
subsequent external reset, asserting these signals for 10 clock cycles or longer resets the
processor. However, an external reset signal that is asserted while the processor is
MOTOROLA
BUS CYCLES
+ 5 VOLTS
NOTES:
RESET
1. Internal start-up time
2. SSP high read in here
3. SSP low read in here
HALT
V CC
CLK
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Figure 5-30. Reset Operation Timing Diagram
Freescale Semiconductor, Inc.
4. PC High read in here
5. PC Low read in here
6. First instruction fetched here
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T
T 4 CLOCKS
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All Control Signals Inactive.
Data Bus in Read Mode:
Bus State Unknown:
1
2
3
4
5
5- 29
6