MC68HC000EI16 Freescale Semiconductor, MC68HC000EI16 Datasheet - Page 78

• Manufacturer Part Number: MC68HC000EI16
• Description: IC MPU 32BIT 16MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000EI16

• Processor Type: M680x0 32-Bit
• Speed: 16MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

• = Signal is negated in this bus state.
5.7 ASYNCHRONOUS OPERATION
To achieve clock frequency independence at a system level, the bus can be operated in
an asynchronous manner. Asynchronous bus operation uses the bus handshake signals
to control the transfer of data. The handshake signals are AS, UDS, LDS, DS (MC68008
only), DTACK, BERR, HALT, AVEC (MC68EC000 only), and VPA (only for M6800
peripheral cycles). AS indicates the start of the bus cycle, and UDS, LDS, and DS signal
valid data for a write cycle. After placing the requested data on the data bus (read cycle)
or latching the data (write cycle), the slave device (memory or peripheral) asserts DTACK
to terminate the bus cycle. If no device responds or if the access is invalid, external control
logic asserts BERR, or BERR and HALT, to abort or retry the cycle. Figure 5-31 shows the
use of the bus handshake signals in a fully asynchronous read cycle. Figure 5-32 shows a
fully asynchronous write cycle.
5-32
Termination in
Conditions of
Table 4-4
Bus Error
4. For an MC68010, return DTACK before data verification. If data is invalid, assert
Normal
Normal
Rerun
Rerun
BERR on the next clock cycle (case 4).
UDS/LDS
DTACK
ADDR
DATA
R/W
AS
Control Signal
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
BERR
BERR
BERR
BERR
BERR
HALT
HALT
HALT
HALT
HALT
Figure 5-31. Fully Asynchronous Read Cycle
Table 5-6.
Freescale Semiconductor, Inc.
For More Information On This Product,
Negated on Rising
BERR
N
•
•
•
•
•
•
•
•
Edge of State
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and
or
or
or
or
or
HALT
none
N+2
•
•
•
•
•
•
Negation Results
Takes bus error trap.
Illegal sequence; usually traps to vector number 0.
Reruns the bus cycle.
May lengthen next cycle.
If next cycle is started, it will be terminated as a bus
error.
Results—Next Cycle
MOTOROLA