MC68HC000EI16 Freescale Semiconductor, MC68HC000EI16 Datasheet - Page 82

• Manufacturer Part Number: MC68HC000EI16
• Description: IC MPU 32BIT 16MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000EI16

• Processor Type: M680x0 32-Bit
• Speed: 16MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

STATE 1
STATE 2
STATE 3
STATE 4
STATE 5
STATE 6
STATE 7
5-36
is the maximum hold time for a low on R/W beyond the initiation of the read
cycle.
is driven externally with an assertion delay defined by parameter #6.
a read cycle, UDS, LDS, and/or DS is also asserted at this time. Parameter
#9 defines the assertion delay for these signals. For a write cycle, the R/W
signal is driven low with a delay defined by parameter #20.
the high-impedance state with the data being written to the accessed
device (in a write cycle). Parameter #23 specifies the data assertion delay.
In a read cycle, no signal is altered in S3.
(during a write cycle) on the rising edge of the clock. As in S2 for a read
cycle, parameter #9 defines the assertion delay from the rising edge of S4
for UDS, LDS, and/or DS. In a read cycle, no signal is altered by the
processor during S4.
Until the falling edge of the clock at the end of S4 (beginning of S5), no
response from any external device except RESET is acknowledged by the
processor. If either DTACK or BERR is asserted before the falling edge of
S4 and satisfies the input setup time defined by parameter #47, the
processor enters S5 and the bus cycle continues. If either DTACK or BERR
is asserted but without meeting the setup time defined by parameter #47,
the processor may recognize the signal and continue the bus cycle; the
result is unpredictable. If neither DTACK nor BERR is asserted before the
next rise of clock, the bus cycle remains in S4, and wait states (complete
clock cycles) are inserted until one of the bus cycle termination is met.
any signal.
set up relative to the falling edge (entering S7). Parameter #27 defines the
minimum period by which the data must precede the falling edge. For a
write operation, the processor changes no signal during S6.
On the falling edge of the clock entering S7, the processor latches data
and negates AS and UDS, LDS, and/or DS during a read cycle. The hold
time for these strobes from this falling edge is specified by parameter #12.
The hold time for data relative to the negation of AS and UDS, LDS, and/or
DS is specified by parameter #29. For a write cycle, only AS and UDS, LDS,
and/or DS are negated; timing parameter #12 also applies.
Entering S1, a low period of the clock, the address of the accessed device
On the rising edge of S2, a high period of the clock, AS is asserted. During
On the falling edge of the clock entering S3, the data bus is driven out of
Entering the high clock period of S4, UDS, LDS, and/or DS is asserted
S5 is a low period of the clock, during which the processor does not alter
S6 is a high period of the clock, during which data for a read operation is
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
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