MPC870CZT133 Freescale Semiconductor, MPC870CZT133 Datasheet

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... To locate published errata or updates for this document, refer to the MPC875/MPC870 product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office. © Freescale Semiconductor, Inc., 2003–2007. All rights reserved. Document Number: MPC875EC Rev. 4, 08/2007 Contents 1 ...

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... Advanced on-chip emulation debug mode • 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Table 1. MPC875/MPC870 Devices Ethernet D Cache 10BaseT 10/100 — 2 Security SCC SMC USB Engine Yes — Table 1) Freescale Semiconductor ...

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... DES, 3DES – Two key (K1, K2, K1) or three key (K1, K2, K3) – ECB and CBC modes for both DES and 3DES — Advanced encryption standard unit (AESU) – Implements the Rijndael symmetric key cipher MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Features 3 ...

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... Independent (can be connected to SCC or SMC) — Allows changes during operation — Autobaud support option • SCC (serial communication controller) — Ethernet/IEEE 802.3® standard, supporting full 10-Mbps operation — HDLC/SDLC MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev GRACEFUL STOP TRANSMIT ) , ENTER HUNT Freescale Semiconductor ...

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... Serial peripheral interface (SPI) — Supports master and slave modes — Supports multiple-master operation on the same bus • Inter-integrated circuit (I — Supports master and slave modes — Supports a multiple-master environment MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 2 C) port Features 5 ...

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... Each watchpoint can generate a break point internally • Normal high and normal low power modes to conserve power • 1.8-V core and 3.3-V I/O operation with 5-V TTL compatibility • The MPC875/MPC870 comes in a 256-pin ball grid array (PBGA) package MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Freescale Semiconductor ...

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... Bus Fast Ethernet Controller DMAs DMAs DMAs FIFOs 10/100 BaseT Media Access Control Parallel Interface MIII/RMII MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Figure 1. 8-Kbyte Unified 32-Entry ITLB Bus 8-Kbyte Data Cache Data MMU 32-Entry DTLB Slave/Master IF 4 Interrupt Parallel I/O ...

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... ROM Timers Port USB Serial Interface Figure 2. MPC870 Block Diagram System Interface Unit (SIU) Memory Controller Internal External Bus Interface Bus Interface Bus Interface Unit Unit System Functions PCMCIA-ATA Interface 8-Kbyte Virtual IDMA and Serial DMAs 2 SMC1 SPI I C Freescale Semiconductor ...

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... V IL GND – 0.7 V Note refers to the clock period associated with the bus clock interface. interface Figure 3. Undershoot/Overshoot Voltage for V MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 3 displays the operating temperatures. Table 2. Maximum Tolerated Ratings V V Difference between V + 20% ...

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... Environment Single-layer board (1s) Four-layer board (2s2p) Single-layer board (1s) Four-layer board (2s2p) Symbol Value Unit T 0 °C A(min °C J(max) T –40 °C A(min) T 100 °C J(max) ). DDH Symbol Value Unit 2 °C θ θJMA θJMA θJMA R 20 θ θJC Ψ Ψ Freescale Semiconductor ...

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... TMS, TRST, DSCK, and in DDH DSDI) Input leakage current (except TMS, TRST, DSCK, and DSDI in pins) 4 Input capacitance MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 5. Power Dissipation (P Frequency Typical 1:1 66 MHz 310 80 MHz 350 2:1 133 MHz 430 = ...

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... DDSYN × where P D DDL DDL I/O NOTE power dissipation is negligible. DDSYN , in °C can be obtained from the following equation: J × – are possible Symbol Min Max V 2.4 — — 0 standard. is the power dissipation of the I/O I/O Freescale Semiconductor Unit V V ...

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... MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor θCA . For instance, the user can change the airflow around θCA × ...

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... V. This restriction applies to power up, power down, and normal operation. MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev can be used to determine the junction temperature with and PLL voltage (V DDL ). The I/O section of the MPC875/MPC870 is supplied with 3.3 V DDH (415) 964-5111 800-854-7179 or 303-397-7956 http://www.jedec.org ), which both operate at a lower DDSYN Freescale Semiconductor ...

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... Table 7. Mandatory Reset Configuration of MPC875/MPC870 Register/Configuration HRCW (Hardware reset configuration word) SIUMCR (SIU module configuration register) MBMR (Machine B mode register) PAPAR (Port A pin assignment register) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor during power up and power down DDH must not exceed 3.465 V DDH V DDH ...

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... GND planes should be used. DD and GND circuits. Pull up all unused inputs or signals that will be DD Value Field (Binary) PADIR[5:9] 0 PADIR[12:13] PBPAR[14:18] 0 PBPAR[20:22] PBDIR[14:8] 0 PBDIR[20:22] PCPAR[4:5] 0 PCPAR[8:9] PCPAR[14] PCDIR[4:5] 0 PCDIR[8:9] PCDIR[14] PDPAR[3:7] 0 PDPAR[9:5] PDDIR[3:7] 0 PDDIR[9:15] and ),” in DDSYN SSSYN SSSYN1 Freescale Semiconductor ...

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... Frequency jitter on EXTCLK B1d CLKOUT phase jitter peak-to-peak for OSCLK ≥ 15 MHz CLKOUT phase jitter peak-to-peak for OSCLK < 15 MHz MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 66 MHz Min 40 20 Table 10, assumes a 50-pF load for maximum delays and Table 10. Bus Operation Timings ...

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... Freescale Semiconductor ...

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... A(0:31) and BADDR(28:30 asserted GPCM ACS = 10, TRLX = 0 (MIN = 0.25 × B1 – 2.00) B24a A(0:31) and BADDR(28:30 asserted GPCM ACS = 11, TRLX = 0 (MIN = 0.50 × B1 – 2.00) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 33 MHz 40 MHz Min Max Min 2.50 15.00 2.50 6.00 — ...

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... Freescale Semiconductor ...

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... WE(0:3)/BS_B[0:3] negated to A(0:31), BADDR(28:30) invalid GPCM write access, TRLX = 0, CSNT = 1. CS negated to A(0:31) invalid GPCM write access, TRLX = 0, CSNT = 1 ACS = 10 or ACS == 11, EBDF = 1 (MIN = 0.375 × B1 – 3.00) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 33 MHz 40 MHz Min Max Min Max 43.50 — ...

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... Max Min Max — 14.19 — ns 6.00 1.50 6.00 ns 10.50 3.13 10.00 ns 8.00 1.50 8.00 ns 10.00 3.13 9.40 ns 12.30 4.69 11.30 ns 6.00 1.50 6.00 ns 10.50 3.13 10.00 ns 8.00 1.50 8.00 ns 10.50 3.13 10.00 ns 12.30 4.49 11.30 ns 6.00 1.50 6.00 ns Freescale Semiconductor ...

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... B1 + 7.00) B40 A(0:31), TSIZ(0:1), RD/WR, BURST valid to CLKOUT rising edge (MIN = 0.00 × 7.00) B41 TS valid to CLKOUT rising edge (setup time) (MIN = 0.00 × 7.00) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 33 MHz 40 MHz Min Max Min 7.60 14.30 6.30 5.60 — ...

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... The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified in Figure 23. MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev MHz 40 MHz 66 MHz Min Max Min Max Min 2.00 — 2.00 — 2.00 — TBD — TBD — Figure 20. 80 MHz Unit Max Min Max — 2.00 — ns TBD — TBD ns Freescale Semiconductor ...

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... Inputs A Maximum output delay specification. B Minimum output hold time. C Minimum input setup time specification. D Minimum input hold time specification. Figure 6 provides the timing for the external clock. CLKOUT MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Figure 5. Control Timing Figure 6. External Clock Timing ...

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... CLKOUT TS, BB TA, BI TEA Figure 8. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev B8a B9 B8b B11 B12 B11 B12a B14 B15 B13 B13a Freescale Semiconductor ...

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... It also applies to normal read accesses under the control of the user-programmable machine (UPM) in the memory controller. CLKOUT TA D[0:31] Figure 10. Input Data Timing in Normal Case MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B16 B17 B16a B17a B16b B17 ...

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... GPCM factors. CLKOUT TS A[0:31] CSx OE WE[0:3] D[0:31] Figure 12. External Bus Read Timing (GPCM Controlled—ACS = 00) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev B20 B21 B11 B12 B8 B22 B25 B28 B18 B23 B26 B19 Freescale Semiconductor ...

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... CSx OE D[0:31] Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT TS A[0:31] CSx OE D[0:31] Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B11 B12 B8 B22a B24 B25 B18 B11 B12 B8 B22b ...

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... Bus Signal Timing CLKOUT B11 TS A[0:31] CSx OE D[0:31] Figure 15. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev B12 B8 B22a B27 B27a B18 B22b B22c B23 B26 B19 Freescale Semiconductor ...

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... GPCM factors. CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31] Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B11 B12 B8 B22 B25 B26 B8 Bus Signal Timing B30 B23 ...

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... Bus Signal Timing CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31] Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev B11 B12 B8 B22 B28b B28d B25 B26 B28a B28c B8 B30a B30c B23 B29c B29g B29a B29f B9 Freescale Semiconductor ...

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... CLKOUT B11 TS A[0:31] CSx WE[0:3] OE D[0:31] Figure 18. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B12 B8 B22 B28b B28d B25 B26 B8 Bus Signal Timing B30b B30d B23 B29e B29i B29d B29h B29b B28a B28c ...

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... UPM. CLKOUT A[0:31] CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 19. External Bus Timing (UPM Controlled Signals) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev B31a B31d B31 B34 B34a B34b B32a B32d B32 B35 B36 B35a B35b B33 B31c B31b B32c B32b B33a Freescale Semiconductor ...

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... UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 21. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor B38 B38 Bus Signal Timing 35 ...

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... Figure 23. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00) Figure 24 provides the timing for the asynchronous external master control signals negation. AS CSx, WE[0:3], OE, GPLx, BS[0:3] Figure 24. Asynchronous External Master—Control Signals Negation Timing MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev B41 B42 B40 B39 B40 B43 B22 B22 Freescale Semiconductor ...

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... Figure 25. Interrupt Detection Timing for External Level Sensitive Lines Figure 26 provides the interrupt detection timing for the external edge-sensitive lines. CLKOUT IRQx Figure 26. Interrupt Detection Timing for External Edge-Sensitive Lines MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 11. Interrupt Timing 1 Characteristic I39 I40 I41 ...

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... Freescale Semiconductor ...

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... PCMCIA access cycle timing for the external bus read. CLKOUT TS A[0:31] REG CE1/CE2 PCOE, IORD ALE D[0:31] Figure 27. PCMCIA Access Cycles Timing External Bus Read MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor P44 P46 P45 P48 P50 P52 P53 B18 Bus Signal Timing P47 ...

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... Figure 28. PCMCIA Access Cycles Timing External Bus Write Figure 29 provides the PCMCIA WAIT signals detection timing. CLKOUT WAITA Figure 29. PCMCIA WAIT Signals Detection Timing MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev P44 P46 P45 P48 P50 P52 P53 B8 P55 P56 P47 P49 P51 P54 P52 B9 Freescale Semiconductor ...

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... PCMCIA output port timing for the MPC875/MPC870. CLKOUT Output Signals HRESET OP2, OP3 Figure 31 provides the PCMCIA input port timing for the MPC875/MPC870. CLKOUT Input Signals MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 13. PCMCIA Port Timing 33 MHz 40 MHz Min Max Min — 19.00 — 1 25.70 — ...

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... D62 D61 D63 Figure 32. Debug Port Clock Input Timing D64 D65 D66 D67 Figure 33. Debug Port Timings All Frequencies Min Max 3 × T CLOCKOUT 1.25 × T CLOCKOUT 0.00 3.00 8.00 5.00 0.00 15.00 0.00 2.00 D62 D63 Freescale Semiconductor Unit — — ...

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... DSDI, DSCK hold time R81 (MIN = 0.00 × 0.00) SRESET negated to CLKOUT rising R82 edge for DSDI and DSCK sample (MIN = 8.00 × B1) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 15. Reset Timing 33 MHz 40 MHz Min Max Min Max — ...

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... CLKOUT SRESET DSCK, DSDI Figure 36. Reset Timing—Debug Port Configuration MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev R71 R76 R73 R74 R75 R69 R79 R77 R78 R70 R82 R80 R80 R81 R81 Freescale Semiconductor ...

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... TCK falling edge to output high impedance J95 Boundary scan input valid to TCK rising edge J96 TCK rising edge to boundary scan input invalid TCK MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 16. JTAG Timing Characteristic J82 J83 J82 J84 Figure 37. JTAG Test Clock Input Timing IEEE 1149 ...

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... Figure 38. JTAG Test Access Port Timing Diagram TCK TRST TCK Output Signals Output Signals Output Signals Figure 40. Boundary Scan (JTAG) Timing Diagram MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev J85 J86 J87 J88 J91 J90 Figure 39. JTAG TRST Timing Diagram J92 J93 J89 J94 J95 J96 Freescale Semiconductor ...

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... SDACK negation delay from clock high 46 TA assertion to rising edge of the clock setup time (applies to external TA) 1 Applies to high-to-low mode (EDM = 1). MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 17. Port C Interrupt Timing Characteristic 35 Figure 41. Port C Interrupt Detection Timing Figure 42 Table 18. IDMA Controller Timing ...

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... CPM Electrical Characteristics CLKO (Output) DREQ (Input) Figure 42. IDMA External Requests Timing Diagram CLKO (Output) TS (Output) R/W (Output) DATA TA (Input) SDACK Figure 43. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Freescale Semiconductor ...

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... TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 44. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 45. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor CPM Electrical Characteristics 45 49 ...

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... CLKO low to TOUT valid MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Table 19. Baud Rate Generator Timing Characteristic Table 20. Timer Timing Characteristic Figure 46. All Frequencies Min Max — — 51 Figure 47. All Frequencies Min Max 10 — 1 — 2 — 3 — Freescale Semiconductor Unit Unit ns clk clk clk ns ...

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... L1CLKB edge to L1ST1 and L1ST2 invalid 80 L1CLKB edge to L1TXDB valid 80A L1TSYNCB valid to L1TXDB valid 81 L1CLKB edge to L1TXDB high impedance 82 L1RCLKB, L1TCLKB frequency (DSC = 1) 83 L1RCLKB, L1TCLKB width low (DSC = 1) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 21. SI Timing Characteristic ...

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... Figure 48. SI Receive Timing Diagram with Normal Clocking (DSC = 0) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Table 21. SI Timing (continued) Characteristic 71a 72 RFSD BIT0 76 78 All Frequencies Unit Min Max — ns — 30.00 ns 1.00 — L1TCLK 42.00 — ns 42.00 — ns — 0. Freescale Semiconductor ...

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... L1RCLKB ( (Input) 82 L1RCLKB ( (Input) 75 L1RSYNCB (Input) 73 L1RXDB (Input) 76 L1ST(2–1) (Output) L1CLKOB (Output) Figure 49. SI Receive Timing with Double-Speed Clocking (DSC = 1) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 72 83a RFSD BIT0 78 84 CPM Electrical Characteristics 79 53 ...

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... CPM Electrical Characteristics L1TCLKB ( (Input) 71 L1TCLKB ( (Input) 73 L1TSYNCB (Input) L1TXDB (Output) L1ST(2–1) (Output) Figure 50. SI Transmit Timing Diagram (DSC = 0) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev TFSD 80a BIT0 Freescale Semiconductor ...

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... L1RCLKB ( (Input) L1RCLKB ( (Input) L1RSYNCB (Input) 73 L1TXDB BIT0 (Output) 80 78a L1ST(2–1) (Output) 84 L1CLKOB (Output) Figure 51. SI Transmit Timing with Double Speed Clocking (DSC = 1) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 72 83a 82 TFSD CPM Electrical Characteristics 79 55 ...

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... CPM Electrical Characteristics MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Figure 52. IDL Timing Freescale Semiconductor ...

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... The ratios SYNCCLK/RCLK3 and SYNCCLK/TCLK3 must be greater or equal to 3/1. 2 Also applies to CD and CTS hold time when they are used as external SYNC signals. MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 22. NMSI External Clock Timing Characteristic 1 2 Table 23. NMSI Internal Clock Timing ...

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... Figure 53. SCC NMSI Receive Timing Diagram TCLK3 102 TxD3 (Output) RTS3 (Output) CTS3 (Input) CTS3 (SYNC Input) Figure 54. SCC NMSI Transmit Timing Diagram MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev 102 101 100 107 102 101 100 103 105 104 108 107 104 107 Freescale Semiconductor ...

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... TXD3 active delay (from TCLK3 rising edge) 132 TXD3 inactive delay (from TCLK3 rising edge) 133 TENA active delay (from TCLK3 rising edge) 134 TENA inactive delay (from TCLK3 rising edge) MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 102 101 100 103 104 107 105 Figure 55 ...

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... RxD3 (Input) RENA(CD3) (Input) Figure 57. Ethernet Receive Timing Diagram MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Table 24. Ethernet Timing (continued) Characteristic 2 2 120 121 124 125 All Frequencies Min Max — 20 — 20 121 123 Last Bit 126 127 Freescale Semiconductor Unit ns ns ...

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... SMTXD active delay (from SMCLK falling edge) 154 SMRXD/SMSYNC setup time 155 RXD1/SMSYNC hold time 1 SYNCCLK must be at least twice as fast as SMCLK. MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 128 121 132 Figure Table 25. SMC Transparent Timing Characteristic CPM Electrical Characteristics ...

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... MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev 152 151 151 150 Note 1 154 155 154 155 Figure 60 Table 26. SPI Master Timing Characteristic 153 and Figure 61. All Frequencies Min Max 4 1024 2 512 15 — 0 — — — — 15 — 15 Freescale Semiconductor Unit t cyc t cyc ...

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... SPICLK ( (Output) 163 162 SPIMISO msb (Input) 167 SPIMOSI msb (Output) Figure 61. SPI Master ( Timing Diagram MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 167 166 160 167 162 166 Data lsb 165 164 166 Data lsb 167 166 ...

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... Table 27. SPI Slave Timing Characteristic 172 182 181 170 181 182 180 Data lsb 179 181 182 Data lsb Figure 63. All Frequencies Min Max 2 — 15 — 15 — 1 — 1 — 20 — 20 — — 50 171 174 178 Undef msb msb Freescale Semiconductor Unit t cyc cyc t cyc ...

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... Start condition setup time 206 Start condition hold time 207 Data hold time 208 Data setup time 209 SDL/SCL rise time MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 172 170 182 181 181 182 180 msb Data 179 176 ...

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... Freescale Semiconductor Unit ns μs Unit ...

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... MII_RX_CLK pulse width low M1_RMII RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR to RMII_REFCLK setup M2_RMII RMII_REFCLK to RMII_RXD[1:0], RMII_CRS_DV, RMII_RX_ERR hold MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 30 lists the USB interface timings. Characteristic 1 Table 31. MII Receive Signal Timing Characteristic USB Electrical Characteristics All Frequencies ...

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... M20_RMII RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup M21_RMII RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising edge MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Table 32. MII Transmit Signal Timing Characteristic M4 Min Max Unit 5 — ns — 35% 65% MII_TX_CLK period 35% 65% MII_TX_CLK period 4 — — ns Freescale Semiconductor ...

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... MII_MDIO (input) to MII_MDC rising edge setup M13 MII_MDIO (input) to MII_MDC rising edge hold M14 MII_MDC pulse width high M15 MII_MDC pulse width low MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Table 33. MII Async Inputs Signal Timing M9 Characteristic FEC Electrical Characteristics ...

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... FEC Electrical Characteristics Figure 68 shows the MII serial management channel timing diagram. MII_MDC (Output) MII_MDIO (Output) MII_MDIO (Input) Figure 68. MII Serial Management Channel Timing Diagram MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev M14 MM15 M10 M11 M12 M13 Freescale Semiconductor ...

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... Freescale Semiconductor Mechanical Data and Ordering Information Temperature (T ) Frequency (MHz) J 0°C to 95° 133 -40°C to 100°C 66 133 Order Number KMPC875ZT66 KMPC870ZT66 MPC875ZT66 MPC870ZT66 KMPC875ZT80 KMPC870ZT80 MPC875ZT80 MPC870ZT80 KMPC875ZT133 KMPC870ZT133 MPC875ZT133 MPC870ZT133 KMPC875CZT66 KMPC870CZT66 MPC875CZT66 MPC870CZT66 KMPC875CZT133 KMPC870CZT133 MPC875CZT133 MPC870CZT133 71 ...

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... A14 A19 A27 A17 VDDH A10 A12 A15 A16 VDDH A2 A8 A11 A13 MII_MDIO PB26 PB27 PC11 TDO PA15 PA10 TCK PB28 PC15 A0 PB29 PB24 TDI TMS PC12 N/C PB30 PB23 PB25 PA14 N/C TRST GND JEDEC Standard — Freescale Semiconductor ...

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... BB C10 IRQ0 M6 IRQ1 P5 IRQ7 N5 CS[0:5] B14, E11, C14, B15, E13, B16 MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Mechanical Data and Ordering Information JEDEC Standard — Pin Number Type Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional Three-state (3 ...

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... Input (3.3 V only) Open-drain Open-drain Analog output Analog input (3.3 V only) Output Input (3.3 V only) Output Output Output Output Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Input (3.3 V only) Freescale Semiconductor ...

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... PA1, MII1-RXD0, T4 RMII1-RXD0, BRGO4 PA0, MII1-RXD1, P6 RMII1-RXD1, TOUT4 PB31, SPISEL, MII1-TXCLK, T5 RMII1-REFCLK MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Mechanical Data and Ordering Information JEDEC Standard (continued) — Pin Number Type Input (3.3 V only) Input (3.3 V only) Bidirectional Three-state (3.3 V only) Bidirectional (3 ...

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... Bidirectional (Optional: open-drain) (5-V tolerant) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional Bidirectional Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (5-V tolerant) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Freescale Semiconductor ...

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... PE14, MII2-TXD0, P8 RMII2-TXD0 TMS T14 TDI, DSDI T13 TCK, DSCK R13 TRST U14 MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Mechanical Data and Ordering Information JEDEC Standard (continued) — Pin Number Type Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) Bidirectional (Optional: open-drain) ...

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... B17, T16, U2, U17 MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev JEDEC Standard (continued) — Pin Number Type Output (5-V tolerant) Input Bidirectional (5-V tolerant) Output (5-V tolerant) Input PLL analog GND PLL analog GND PLL analog V DD Power Power Power No connect Freescale Semiconductor ...

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... DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. Note: Solder sphere composition is 95.5%Sn 45%Ag 0.5%Cu for MPC875/MPC870VRXXX. Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC875/MPC870ZTXXX. Figure 70. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Mechanical Data and Ordering Information 79 ...

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... Put the pin numbers in footnotes by the maximum currents in Table 6. Changed 22 and 41 in the Timing. Put TBD in the Thermal table. MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Table 37. Document Revision History Changes 2 C. Put in the new reset configuration, corrected the USB timing. Freescale Semiconductor ...

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... In Table • In Figure MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Changes 5, changed all reference voltage measurement points from 0.2 and 0 50% level. 18, changed num 46 description to read, “TA assertion to rising edge ...” 43, changed TA to reflect the rising edge of the clock. ...

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... Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev Freescale Semiconductor ...

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... THIS PAGE INTENTIONALLY LEFT BLANK MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor Document Revision History 83 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...