PRIXP423BB Intel, PRIXP423BB Datasheet - Page 33

• Manufacturer Part Number: PRIXP423BB
• Description: IC NETWRK PROCESSR 266MHZ 492BGA
• Manufacturer: Intel

Specifications of PRIXP423BB

• Processor Type: Network
• Features: XScale Core
• Speed: 266MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 869741

Datasheet
Table 6.
PCI Controller (Sheet 1 of 2)
PCI_AD[31:0]
PCI_CBE_N[3:0]
PCI_PAR
PCI_FRAME_N
PCI_TRDY_N
PCI_IRDY_N
PCI_STOP_N
PCI_PERR_N
PCI_SERR_N
PCI_DEVSEL_N
PCI_IDSEL
PCI_REQ_N[3:1]
PCI_REQ_N[0]
PCI_GNT_N[3:1]
†
For a legend of the Type codes, see
Name
Reset
Power
On
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Intel
†
Reset
®
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
IXP42X Product Line and IXC1100 Control Plane Processor
Table 4 on page
†
Type
I/OD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
†
PCI Address/Data bus used to transfer address and bidirectional data to
and from multiple PCI devices.
Should be pulled low with a 10-KΩ resistor when not being utilized in the
system.
PCI Command/Byte Enables is used as a command word during PCI address
cycles and as byte enables for data cycles.
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI Parity used to check parity across the 32 bits of PCI_AD and the
four bits of PCI_CBE_N.
Should be pulled low with a 10-KΩ resistor when not being utilized in the
system.
PCI Cycle Frame used to signify the beginning and duration of a
transaction. The signal will be inactive prior to or during the final data
phase of a given transaction.
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI Target Ready informs that the target of the PCI bus is ready to
complete the current data phase of a given transaction.
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI Initiator Ready informs the PCI bus that the initiator is ready to
complete the transaction.
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI Stop indicates that the current target is requesting the current initiator
to stop the current transaction.
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI Parity Error asserted when a PCI parity error is detected — between the
PCI_PAR and associated information on the PCI_AD bus and PCI_CBE_N —
during all PCI transactions, except for Special Cycles. The agent receiving
data will drive this signal.
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI System Error asserted when a parity error occurs on special cycles or
any other error that will cause the PCI bus not to function properly. This
signal can function as an input or an open drain output.
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI Device Select:
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI Initialization Device Select is a chip select during configuration reads
and writes.
Should be pulled low with a 10-KΩ resistor when not being utilized in the
system.
PCI arbitration request: Used by the internal PCI arbiter to allow an agent
to request the PCI bus.
Should be pulled high with a 10-KΩ resistor when not being utilized in the
system.
PCI arbitration request:
Should be pulled high with a 10-KΩ resistor, when the PCI bus is not being
utilized in the system.
PCI arbitration grant: Generated by the internal PCI arbiter to allow an
agent to claim control of the PCI bus.
30.
•
•
•
•
When used as an output, PCI_DEVSEL_N indicates that device has
decoded that address as the target of the requested transaction.
When used as an input, PCI_DEVSEL_N indicates if any device on
the PCI bus exists with the given address.
When configured as an input (PCI arbiter enabled), the internal PCI
arbiter will allow an agent to request the PCI bus.
When configured as an output (PCI arbiter disabled), the pin will be
used to request access to the PCI bus from an external arbiter.
Functional Signal Descriptions
Description
33