MC68HC000EI20 Freescale Semiconductor, MC68HC000EI20 Datasheet - Page 183

no-image

MC68HC000EI20

Manufacturer Part Number
MC68HC000EI20
Description
IC MPU 16BIT 20MHZ 68-PLCC
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC000EI20

Processor Type
M680x0 32-Bit
Speed
20MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC000EI20
Manufacturer:
TI
Quantity:
14 500
Part Number:
MC68HC000EI20
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68HC000EI20R2
Manufacturer:
FREESCAL
Quantity:
8 831
Of these five bus cycles, only two move the data. However, the MC68010 has a two-word
prefetch queue in addition to the one-word instruction decode register. The loop mode
uses the prefetch queue and the instruction decode register to eliminate the instruction
fetch cycles. The processor places the MOVE instruction in the instruction decode register
and the two words of the DBEQ instruction in the prefetch queue. With no additional
opcode fetches, the processor executes these two instructions as required to move the
entire block or to move all nonzero words that precede a zero.
The MC68010 enters the loop mode automatically when the conditions for loop mode
operation are met. Entering the loop mode is transparent to the programmer. The
conditions are that the loop count and branch condition of the DBcc instruction must result
in looping, the branch displacement must be minus four, and the branch must be to a one-
word loop mode instruction preceding the DBcc instruction. The looped instruction and the
first word of the DBcc instruction are each fetched twice when the loop is entered. When
the processor fetches the looped instruction the second time and determines that the
looped instruction is a loop mode instruction, the processor automatically enters the loop
mode, and no more instruction fetches occur until the count is exhausted or the loop
condition is true.
In addition to the normal termination conditions for the loop, several abnormal conditions
cause the MC68010 to exit the loop mode. These abnormal conditions are as follows:
Any pending interrupt is taken after each execution of the DBcc instruction, but not after
each execution of the looped instruction. Taking an interrupt exception terminates the loop
mode operation; loop mode operation can be restarted on return from the interrupt
handler. While the T bit is set, a trace exception occurs at the end of both the looped
instruction and the DBcc instruction, making loop mode unavailable while tracing is
enabled. A reset operation aborts all processing, including loop mode processing. A bus
error during loop mode operation is handled the same as during other processing;
however, when the return from exception (RTE) instruction continues execution of the
looped instruction, the three-word loop is not fetched again.
Table A-1 lists the loop mode instructions of the MC68010. Only one-word versions of
these instructions can operate in the loop mode. One-word instructions use the three
address register indirect modes: (An), (An)+, and –(An).
A-2
1. Fetch the MOVE instruction.
2. Fetch the DBEQ instruction.
3. Read the operand at the address in A0.
4. Write the operand at the address in A1.
5. Fetch the displacement word of the DBEQ instruction.
• Interrupts
• Trace Exceptions
• Reset Operations
• Bus Errors
M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA

Related parts for MC68HC000EI20