MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet
MC68340AG16E
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MC68340AG16E Summary of contents
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... Freescale Semiconductor, Inc. µ MOTOROLA Integrated Processor with DMA ©MOTOROLA INC., 1992 For More Information On This Product, MC68340 User’s Manual Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others ...
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... Freescale Semiconductor, Inc. The complete documentation package for the MC68340 consists of the MC68340UM/AD, MC68340 Integrated Processor with DMA User’s Manual , M68000PM/AD, MC68000 Family Programmer’s Reference Manual, and the MC68340P/D, MC68340 Integrated Processor with DMA Product Brief . The MC68340 Integrated with DMA Processor User’s Manual describes the programming, capabilities, registers, and operation of the MC68340 ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW TABLE OF CONTENTS Paragraph Number 1.1 M68300 Family.................................................................................................. 1-2 1.1.1 Organization .................................................................................................. 1-3 1.1.2 Advantages.................................................................................................... 1-3 1.2 Central Processor Unit..................................................................................... 1-3 1.2.1 CPU32 ............................................................................................................ 1-4 1.2.2 Background Debug Mode........................................................................... 1-4 1.3 On-Chip Peripherals ........................................................................................ 1-5 1.3.1 System Integration Module......................................................................... 1-5 1 ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW TABLE OF CONTENTS (Continued) Paragraph Number 2.7 Bus Control Signals ......................................................................................... 2-6 2.7.1 Data and Size Acknowledge ( DSACK1 , DSACK0 )................................ 2-6 Address Strobe ( AS ).................................................................................... 2-6 2.7.2 Data Strobe ( DS )........................................................................................... 2-7 2.7.3 2.7.4 Transfer Size (SIZ1, SIZ0) .......................................................................... 2-7 Read/Write (R/ W )........................................................................................... 2-7 2 ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW TABLE OF CONTENTS (Continued) Paragraph Number 2.15 Test Signals....................................................................................................... 2-13 2.15.1 Test Clock (TCK)........................................................................................... 2-13 2.15.2 Test Mode Select (TMS).............................................................................. 2-13 2.15.3 Test Data In (TDI).......................................................................................... 2-13 2.15.4 Test Data Out (TDO)..................................................................................... 2-13 2.16 Synthesizer Power (V 2.17 System Power and Ground (V 2 ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW TABLE OF CONTENTS (Continued) Paragraph Number 3.4 CPU Space Cycles........................................................................................... 3-21 3.4.1 Breakpoint Acknowledge Cycle................................................................. 3-22 3.4.2 LPSTOP Broadcast Cycle........................................................................... 3-23 3.4.3 Module Base Address Register Access.................................................... 3-27 3.4.4 Interrupt Acknowledge Bus Cycles............................................................ 3-27 3.4.4.1 Interrupt Acknowledge Cycle—Terminated Normally........................ 3-27 3 ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW TABLE OF CONTENTS (Continued) Paragraph Number 4.2.4.2 Global Chip Select Operation ................................................................ 4-14 4.2.5 External Bus Interface Operation............................................................... 4-15 4.2.5.1 Port A........................................................................................................... 4-15 4.2.5.2 Port B........................................................................................................... 4-16 4.2.6 Low-Power Stop ........................................................................................... 4-17 4.2.7 Freeze............................................................................................................. 4-17 4.3 Programming Model......................................................................................... 4-18 4.3.1 Module Base Address Register (MBAR) ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW TABLE OF CONTENTS (Continued) Paragraph Number 5.1.4 Vector Base Register.................................................................................... 5-4 5.1.5 Exception Handling...................................................................................... 5-4 5.1.6 Addressing Modes........................................................................................ 5-5 5.1.7 Instruction Set................................................................................................ 5-5 5.1.7.1 Table Lookup and Interpolate Instructions........................................... 5-7 5.1.7.2 Low-Power STOP Instruction ................................................................. 5-7 5.1.8 Processing States ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW TABLE OF CONTENTS (Continued) Paragraph Number 5.4.2.3 Changing Privilege Level........................................................................ 5-39 5.5 Exception Processing ...................................................................................... 5-39 5.5.1 Exception Vectors......................................................................................... 5-40 5.5.1.1 Types of Exceptions ................................................................................. 5-41 5.5.1.2 Exception Processing Sequence .......................................................... 5-41 5.5.1.3 Exception Stack Frame............................................................................ 5-42 5.5.1.4 Multiple Exceptions .................................................................................. 5-42 5 ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW TABLE OF CONTENTS (Continued) Paragraph Number 5.6.1.3 On-Chip Hardware Breakpoint Overview............................................. 5-64 5.6.2 Background Debug Mode........................................................................... 5-65 5.6.2.1 Enabling BDM ........................................................................................... 5-65 5.6.2.2 BDM Sources ............................................................................................ 5-66 5.6.2.2.1 External BKPT Signal.......................................................................... 5-66 5.6.2.2.2 BGND Instruction .................................................................................. 5-66 5.6.2.2.3 Double Bus Fault. ................................................................................. 5-66 5 ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW TABLE OF CONTENTS (Continued) Paragraph Number 5.7.1.3 Bus Controller Resources ....................................................................... 5-89 5.7.1.3.1 Prefetch Controller................................................................................ 5-90 5.7.1.3.2 Write Pending Buffer. ........................................................................... 5-90 5.7.1.3.3 Microbus Controller.............................................................................. 5-91 5.7.1.4 Instruction Execution Overlap................................................................. 5-91 5.7.1.5 Effects of Wait States................................................................................ 5-92 5.7.1.6 Instruction Execution Time Calculation ................................................ 5-92 5 ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW TABLE OF CONTENTS (Continued) Paragraph Number 6.3.2.2 External Cycle Steal Mode ..................................................................... 6-5 6.4 Data Transfer Modes........................................................................................ 6-6 6.4.1 Single-Address Mode.................................................................................. 6-6 6.4.1.1 Single-Address Read............................................................................... 6-7 6.4.1.2 Single-Address Write............................................................................... 6-9 6.4.2 Dual-Address Mode ..................................................................................... 6-12 6.4.2.1 Dual-Address Read.................................................................................. 6-12 6 ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW TABLE OF CONTENTS (Continued) Paragraph Number 7.1.5 Comparison of Serial Module to MC68681............................................. 7-4 7.2 Serial Module Signal Definitions................................................................... 7-4 7.2.1 Crystal Input or External Clock (X1) .......................................................... 7-5 7.2.2 Crystal Output (X2) ....................................................................................... 7-5 7.2.3 External Input (SCLK).................................................................................. 7-6 7.2.4 Channel A Transmitter Serial Data Output (TxDA)................................. 7-6 7 ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW TABLE OF CONTENTS (Continued) Paragraph Number 7.4.1.2 Interrupt Level Register (ILR).................................................................. 7-21 7.4.1.3 Interrupt Vector Register (IVR)................................................................ 7-21 7.4.1.4 Mode Register 1 (MR1)............................................................................ 7-22 7.4.1.5 Status Register (SR)................................................................................. 7-24 7.4.1.6 Clock-Select Register (CSR).................................................................. 7-26 7.4.1.7 Command Register (CR) ......................................................................... 7-27 7 ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW TABLE OF CONTENTS (Continued) Paragraph Number 8.3.3 Variable Duty-Cycle Square-Wave Generator........................................ 8-9 8.3.4 Variable-Width Single-Shot Pulse Generator......................................... 8-10 8.3.5 Pulse-Width Measurement.......................................................................... 8-12 8.3.6 Period Measurement.................................................................................... 8-13 8.3.7 Event Count ................................................................................................... 8-14 8.3.8 Timer Bypass................................................................................................. 8-16 8.3.9 Bus Operation................................................................................................ 8-17 8 ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW TABLE OF CONTENTS (Concluded) Paragraph Number 10.1.2 Reset Circuitry ............................................................................................. 10-3 10.1.3 SRAM Interface ........................................................................................... 10-3 10.1.4 ROM Interface.............................................................................................. 10-4 10.1.5 Serial Interface............................................................................................ 10-4 10.2 Memory Interface Information....................................................................... 10-5 10.2.1 Using an 8-Bit Boot ROM........................................................................... 10-5 10.2.2 Access Time Calculations......................................................................... 10-6 10 ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW LIST OF ILLUSTRATIONS Figure Number 1-1 Block Diagram......................................................................................................... 1-1 2-1 Functional Signal Groups ..................................................................................... 2-1 3-1 Input Sample Window............................................................................................ 3-2 3-2 MC68340 Interface to Various Port Sizes.......................................................... 3-7 3-3 Long-Word Operand Read Timing from 8-Bit Port............................................ 3-11 3-4 Long-Word Operand Write Timing to 8-Bit Port ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW LIST OF ILLUSTRATIONS (Continued) Figure Number 4-5 MC68340 Crystal Oscillator.................................................................................. 4-10 4-6 Clock Block Diagram for External Oscillator Operation................................... 4-11 4-7 Full Interrupt Request Multiplexer........................................................................ 4-16 4-8 SIM40 Programming Model.................................................................................. 4-19 5-1 CPU32 Block Diagram........................................................................................... 5-3 5-2 Loop Mode Instruction Sequence ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW LIST OF ILLUSTRATIONS (Continued) Figure Number 6-1 DMA Block Diagram............................................................................................... 6-1 6-2 Single-Address Transfers ..................................................................................... 6-3 6-3 Dual-Address Transfer........................................................................................... 6-3 6-4 DMA External Connections to Serial Module.................................................... 6-6 6-5 Single-Address Read Timing (External Burst) .................................................. 6-8 6-6 Single-Address Read Timing (Cycle Steal)....................................................... 6-9 6-7 Single-Address Write Timing (External Burst) ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW LIST OF ILLUSTRATIONS (Continued) Figure Number 9-3 Output Latch Cell (O.Latch)................................................................................... 9-7 9-4 Input Pin Cell (I.Pin)................................................................................................ 9-7 9-5 Active-High Output Control Cell (IO.Ctl1)........................................................... 9-8 9-6 Active-Low Output Control Cell (IO.Ctl0)............................................................ 9-8 9-7 Bidirectional Data Cell (IO.Cell)........................................................................... 9-9 9-8 General Arrangement for Bidirectional Pins ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW LIST OF ILLUSTRATIONS (Concluded) Figure Number 11-16 Serial Module Asynchronous Mode Timing (X1)............................................ 11-23 11-17 Serial Module Asynchronous Mode Timing (SCLK–16X)............................ 11-23 11-18 Serial Module Synchronous Mode Timing Diagram ..................................... 11-23 11-19 Test Clock Input Timing Diagram....................................................................... 11-25 11-20 Boundary Scan Timing Diagram ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW Table Number 2-1 Signal Index............................................................................................................. 2-2 2-2 Address Space Encoding ..................................................................................... 2-5 2-3 DSACK Encoding................................................................................................. 2-6 2-4 SIZx Signal Encoding............................................................................................ 2-7 2-5 Signal Summary..................................................................................................... 2-14 3-1 SIZx Signal Encoding............................................................................................ 3-3 3-2 Address Space Encoding ..................................................................................... 3-3 3-3 DSACK Encoding ...
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... Freescale Semiconductor, Inc. 11/2/95 SECTION 1: OVERVIEW LIST OF TABLES (Continued) Table Number 5-15 8-Bit Independent Variable Entries ..................................................................... 5-33 5-16 Exception Vector Assignments............................................................................. 5-40 5-17 Exception Priority Groups...................................................................................... 5-43 5-18 Tracing Control........................................................................................................ 5-50 5-19 BDM Source Summary.......................................................................................... 5-67 5-20 Polling the BDM Entry Source.............................................................................. 5-68 5-21 CPU Generated Message Encoding ...
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... Freescale Semiconductor, Inc. SECTION 1 DEVICE OVERVIEW The MC68340 is a high-performance 32-bit integrated processor with direct memory access (DMA), combining an enhanced M68000-compatible processor, 32-bit DMA, and other peripheral subsystems on a single integrated circuit. The MC68340 CPU32 delivers 32-bit CISC processor performance from a lower cost 16-bit memory system. The combination of peripherals offered in the MC68340 can be found in a diverse range of microprocessor-based systems, including embedded control and general computing ...
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... Freescale Semiconductor, Inc. The primary features of the MC68340, illustrated in Figure 1-1, are as follows: • High Functional Integration on a Single Piece of Silicon • CPU32—MC68020-Derived 32-Bit Central Processor Unit — Upward Object-Code Compatible with MC68000 and MC68010 — Additional MC68020 Instructions and Addressing Modes — ...
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... Freescale Semiconductor, Inc. 1.1.1 Organization The M68300 family of integrated processors and controllers is built on an M68000 core processor, an on-chip bus, and a selection of intelligent peripherals appropriate for a set of applications. The CPU32 is a powerful central processor with nearly the performance of the MC68020. A system integration module incorporates the external bus interface and ...
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... Freescale Semiconductor, Inc. 1.2.1 CPU32 The CPU32 is an M68000 family processor specially designed for use as a 32-bit core processor and for operation over the intermodule bus (IMB). Designers used the MC68020 as a model and included advances of the later M68000 family processors, resulting in an instruction execution performance of 4 MIPS (VAX-equivalent ...
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... Freescale Semiconductor, Inc. Commands are received over a dedicated, high-speed, full-duplex serial interface. Commands allow the manual reading or writing of CPU32 registers, reading or writing of external memory locations, and diversion to user-specified patch code. This background debug mode permits a much simpler emulation environment while leaving the processor chip in the target system, running its own debugging operations ...
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... Freescale Semiconductor, Inc. memory system to signal the CPU32 or DMA when the transfer is complete and to note the number of bits in the transfer. An external master can arbitrate for the bus using a three-line handshaking interface. 1.3.1.2 SYSTEM CONFIGURATION AND PROTECTION. The M68000 family of processors is designed with the concept of providing maximum system safeguards. ...
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... Freescale Semiconductor, Inc. 1.3.1.7 IEEE 1149.1 TEST ACCESS PORT. To aid in system diagnostics, the MC68340 includes dedicated user-accessible test logic that is fully compliant with the IEEE 1149.1 standard for boundary scan testability, often referred to as JTAG (Joint Test Action Group). 1.3.2 Direct Memory Access Module ...
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... Freescale Semiconductor, Inc. Each communication channel is completely independent. Data formats can bits with even, odd parity and stop bits 1/16 increments. Four-byte receive buffers and two-byte transmit buffers minimize CPU service calls. A wide variety of error detection and maskable interrupt capability is provided on each channel. Full-duplex, autoecho loopback, local loopback, and remote loopback modes can be selected ...
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... Freescale Semiconductor, Inc. requires only a 3.3-V power supply, reduces current consumption by 40–60% in all modes of operation (as well as reducing noise emissions). The MC68340 has many additional methods of dynamically controlling power consumption during operation. The frequency of operation can be lowered under software control to reduce current consumption when performance is less critical. Idle internal peripheral modules can be turned off to save power (5– ...
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... Freescale Semiconductor, Inc. 1.7 MORE INFORMATION The following table lists available documentation related to the MC68340: Document Number BR1114/D MC68340/D MC68340UM/AD M68000PM/AD AN1063/D AN453 BR573/D BR729/D BR1407/D 1-10 For More Information On This Product, Document Name M68300 Integrated Processor Family MC68340 Technical Summary ...
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... Freescale Semiconductor, Inc. SECTION 2 SIGNAL DESCRIPTIONS This section contains brief descriptions of the MC68340 input and output signals in their functional groups as shown in Figure 2-1. A31/PORT A7/IACK7 A30/PORT A6/IACK6 A29/PORT A5/IACK5 A28/PORT A4/IACK4 PORT A A27/PORT A3/IACK3 A26/PORT A2/IACK2 A25/PORT A1/IACK1 A24/PORT A0 A23–A0 D15– ...
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... Freescale Semiconductor, Inc. 2.1 SIGNAL INDEX The input and output signals for the MC68340 are listed in Table 2-1. The name, mnemonic, and brief functional description are presented. For more detail on each signal, refer to the signal paragraph. Guaranteed timing specifications for the signals listed in Table 2-1 can be found in Section 11 Electrical Characteristics ...
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... Freescale Semiconductor, Inc. Table 2-1. Signal Index (Continued) Signal Name Mnemonic Clock Mode Select/ MODCK Port B0 Instruction Fetch/ IFETCH /DSI Development Serial In IPIPE/ DSO Instruction Pipe/ Development Serial Out Breakpoint/Development BKPT /DSCLK Serial Clock Freeze FREEZE Transmit Data TxDA, TxDB CTSA, CTSB ...
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... Freescale Semiconductor, Inc. The terms assert and negate are used throughout this section to avoid confusion when dealing with a mixture of active-low and active-high signals. The term assert or assertion indicates that a signal is active or true, independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false ...
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... Freescale Semiconductor, Inc. last falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The MC68340 places the data on the data bus approximately one-half clock cycle after AS is asserted in a write cycle. ...
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... Freescale Semiconductor, Inc. Port B4, B2, B1, AVEC This signal group functions as three bits of parallel I/O and the autovector input. AVEC requests an automatic vector during an interrupt acknowledge cycle. 2.6 INTERRUPT REQUEST LEVEL (IRQ7, IRQ6, IRQ5, IRQ3) These pins can be programmed to be either prioritized interrupt request lines or port B parallel I/O ...
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... Freescale Semiconductor, Inc. 2.7.3 Data Strobe ( output timing signal that applies to the data bus. For a read cycle, the MC68340 asserts DS and AS simultaneously to signal the external device to place data on the bus. For a write cycle, DS signals to the external device that the data to be written is valid. The MC68340 asserts DS approximately one clock cycle after the assertion of AS during a write cycle ...
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... Freescale Semiconductor, Inc. 2.8.4 Read-Modify-Write Cycle ( RMC ) This output signal identifies the bus cycle as part of an indivisible read-modify-write operation. It remains asserted during all bus cycles of the read-modify-write operation to indicate that bus ownership cannot be transferred. 2.9 EXCEPTION CONTROL SIGNALS These signals are used by the MC68340 to recover from an exception. ...
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... Freescale Semiconductor, Inc. 2.10.2 Crystal Oscillator (EXTAL, XTAL) These two pins are the connections for an external crystal to the internal oscillator circuit external oscillator is used, it should be connected to EXTAL, with XTAL left open. 2.10.3 External Filter Capacitor (XFC) This pin is used to add an external capacitor to the filter circuit of the phase-locked loop. ...
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... Freescale Semiconductor, Inc. IPIPE This active-low output signal is used to track movement of words through the instruction pipeline. DSO This development serial output signal helps to provide serial communications for background debug mode. 2.11.3 Breakpoint (BKPT) This pin functions as BKPT in normal operation and as DSCLK in background debug mode ...
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... Freescale Semiconductor, Inc. 2.13 SERIAL MODULE SIGNALS The following signals are used by the serial module for data and clock signals. See Section 7 Serial Module for more information on these signals. 2.13.1 Serial Crystal Oscillator (X2, X1) These pins furnish the connection to a crystal or external clock, which must be supplied when using the baud rate generator. An external clock is connected to the X1 pin ...
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... Freescale Semiconductor, Inc. T RDYA When used for this function, this signal reflects the complement of the status of bit 2 of the channel A status register. This signal can be used to control parallel data flow by acting as an interrupt to indicate when the transmitter contains a character. OP6 When used for this function, this output is controlled by bit 6 in the output port data registers ...
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... Freescale Semiconductor, Inc. 2.15 TEST SIGNALS The following signals are used with the on-board test logic defined by the IEEE 1149.1 standard. See Section 9 IEEE 1149.1 Test Access Port for more information on the use of these signals. 2.15.1 Test Clock (TCK) This input provides a clock for on-board test logic defined by the IEEE 1149.1 standard. ...
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... Freescale Semiconductor, Inc. Signal Name Address Bus Address Bus Port A7–A0/ Interrupt Acknowledge Data Bus Function Codes Chip Select 3/Interrupt Request Level/Port B4, B2, B1 Chip Select 0/Autovector Bus Request Bus Grant Bus Grant Acknowledge Data and Size Acknowledge Read-Modify-Write Cycle Address Strobe ...
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... Freescale Semiconductor, Inc. Table 2-5. Signal Summary (Continued) Signal Name Transmit Data Clear-to-Send Request-to-Send/ OP1, OP0 Serial Clock Transmitter Ready/OP6 Receiver Ready/ FIFO Full/OP4 DMA Request DMA Acknowledge DMA Done Timer Gate Timer Input Timer Output Test Clock Test Mode Select ...
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... Freescale Semiconductor, Inc. SECTION 3 BUS OPERATION This section provides a functional description of the bus, the signals that control it, and the bus cycles provided for data transfer operations. It also describes the error and halt conditions, bus arbitration, and reset operation. Operation of the external bus is the same whether the MC68340 or an external device is the bus master ...
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... Freescale Semiconductor, Inc. the sample window input makes a transition during the window time period, the level recognized by the MC68340 is not predictable; however, the MC68340 always resolves the latched level to either a logic high or low before using it. In addition to meeting input setup and hold times for deterministic operation, all input signals must obey the protocols described in this section ...
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... Freescale Semiconductor, Inc. Table 3-1. SIZx Signal Encoding SIZ1 3.1.2 Function Code Signals FC3–FC0 are outputs that indicate one of 16 address spaces to which the address applies. Fifteen of these spaces are designated as either user or supervisor, program or data, and normal or direct memory access (DMA) spaces. One other address space is designated as CPU space to allow the CPU32 to acquire specific control information not normally associated with read or write bus cycles. FC3– ...
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... Freescale Semiconductor, Inc. 3.1.3 Address Bus (A31–A0) These signals are outputs that define the address of the byte (or the most significant byte transferred during a bus cycle. The MC68340 places the address on the bus at the beginning of a bus cycle. The address is valid while AS is asserted. ...
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... Freescale Semiconductor, Inc. 3.1.7.2 BUS ERROR ( BERR ). This signal is also a bus cycle termination indicator and can be used in the absence of DSACK to indicate a bus error condition. BERR can also be asserted in conjunction with DSACK to indicate a bus error condition, provided it meets the appropriate timing described in this section and in Section 11 Electrical Characteristics ...
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... Freescale Semiconductor, Inc. For example, if the MC68340 is executing an instruction that reads a long-word operand from a 16-bit port, the MC68340 latches the 16 bits of valid data and runs another bus cycle to obtain the other 16 bits. The operation from an 8-bit port is similar, but requires four read cycles. The addressed device uses DSACK to indicate the port width. For instance, a 16-bit device always returns DSACK for a 16-bit port (regardless of whether the bus cycle is a byte or word operation) ...
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... Freescale Semiconductor, Inc. Case Transfer Case (a) Byte to Byte (b) Byte to Word (Even) (c) Byte to Word (Odd) (d) Word to Byte (Aligned) (e) Word to Word (Aligned) (f) Long Word to Byte (Aligned) (g) Long Word to Word (Aligned) NOTES: 1. Operands in parentheses are ignored by the MC68340 during read cycles 3-byte to byte transfer does occur as the second byte transfer of a long-word to byte port transfer. ...
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... Freescale Semiconductor, Inc. BYTE OPERAND OP0 7 DATA BUS D15 OP0 CYCLE 1 For a read operation, the slave responds by placing data on bits 15–8 of the data bus, asserting DSACK0 and negating DSACK1 to indicate an 8-bit port. The MC68340 then reads the operand byte from bits 15–8 and ignores bits 7–0. ...
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... Freescale Semiconductor, Inc. 3.2.3.3 BYTE OPERAND TO 16-BIT PORT, ODD (A0 = 1). The MC68340 drives the address bus with the desired address and the SIZx pins to indicate a single-byte operand. BYTE OPERAND DATA BUS D15 CYCLE 1 (OP0) For a read operation, the slave responds by placing data on bits 7–0 of the data bus and asserting DSACK1 to indicate a 16-bit port. The MC68340 then reads the operand byte from bits 7– ...
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... Freescale Semiconductor, Inc. 3.2.3.5 WORD OPERAND TO 16-BIT PORT, ALIGNED. The MC68340 drives the address bus with the desired address and the size pins to indicate a word operand. WORD OPERAND OP0 15 DATA BUS D15 CYCLE 1 OP0 For a read operation, the slave responds by placing the data on bits 15–0 of the data bus and asserting DSACK1 to indicate a 16-bit port ...
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... Freescale Semiconductor, Inc CLKOUT A31–A0 FC3–FC0 R SIZ0 4 BYTES SIZ1 DSACK0 DSACK1 D15–D8 OP0 D7–D0 BYTE READ Figure 3-3. Long-Word Operand Read Timing from 8-Bit Port MOTOROLA For More Information On This Product BYTES 2 BYTES OP1 BYTE BYTE READ READ LONG-WORD OPERAND READ FROM 8-BIT BUS MC68340 USER’ ...
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... Freescale Semiconductor, Inc CLKOUT A31–A0 FC3–FC0 R SIZ0 4 BYTES SIZ1 DSACK0 DSACK1 OP0 D15–D8 (OP1) D7–D0 WRITE Figure 3-4. Long-Word Operand Write Timing to 8-Bit Port 3.2.3.7 LONG-WORD OPERAND TO 16-BIT PORT, ALIGNED. Figure 3-5 shows both long-word and word read and write timing to a 16-bit port. ...
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... Freescale Semiconductor, Inc CLKOUT A31–A0 FC3–FC0 R SIZ0 2 BYTES 4 BYTES SIZ1 DSACK0 DSACK1 OP0 D15–D8 OP1 D7–D0 LONG WORD READ FROM 16-BIT BUS Figure 3-5. Long-Word and Word Read and Write Timing—16-Bit Port The MC68340 drives the address bus with the desired address and drives the SIZx pins to indicate a long-word operand. For a read operation, the slave responds by placing the two most significant bytes of the operand on bits 15– ...
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... Freescale Semiconductor, Inc. 3.2.4 Bus Operation The MC68340 bus is asynchronous, allowing external devices connected to the bus to operate at clock frequencies different from the clock for the MC68340. Bus operation uses the handshake lines ( AS, DS, DSACK1/DSACK0, BERR , and HALT ) to control data transfers. AS signals a valid address on the address bus, and DS is used as a condition for valid data on a write cycle ...
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... Freescale Semiconductor, Inc system asserts DSACK for the required window around the falling edge of S2 and obeys the proper bus protocol by maintaining DSACK (and/or BERR / HALT ) until and throughout the clock edge that negates AS (with the appropriate asynchronous input hold time), no wait states are inserted. The bus cycle runs at its maximum speed for bus cycles terminated with DSACK (three clocks per cycle) ...
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... Freescale Semiconductor, Inc. 3.3 DATA TRANSFER CYCLES The transfer of data between the MC68340 and other devices involves the following signals: • Address Bus A31–A0 • Data Bus D15–D0 • Control Signals The address bus and data bus are parallel, nonmultiplexed buses. The bus master moves data on the bus by issuing control signals, and the bus uses a handshake protocol to ensure correct movement of the data ...
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... Freescale Semiconductor, Inc. State 0—The read cycle starts in state 0 (S0). During S0, the MC68340 places a valid address on A31–A0 and valid function codes on FC3–FC0. The function codes select the address space for the cycle. The MC68340 drives R/ W high for a read cycle. SIZ1/SIZ0 become valid, indicating the number of bytes requested for transfer. State 1— ...
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... Freescale Semiconductor, Inc. 3.3.2 Write Cycle During a write cycle, the MC68340 transfers data to memory or a peripheral device. Figure 3 flowchart of a word write cycle. BUS MASTER ADDRESS DEVICE 1. SET R/W TO WRITE 2. DRIVE ADDRESS ON A31–A0 3. DRIVE FUNCTION CODE ON FC3–FC0 4. DRIVE SIZE PINS FOR OPERAND SIZE 5. ASSERT AS 6. PLACE DATA ON D15– ...
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... Freescale Semiconductor, Inc. State 4—The MC68340 issues no new control signals during S4. State 5—The MC68340 negates AS and DS during S5. It holds the address and data valid during S5 to provide address hold time for memory systems SIZ1/SIZ0, and FC3– FC0 also remain valid throughout S5. The external device must keep DSACK asserted until it detects the negation (whichever it detects first) ...
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... Freescale Semiconductor, Inc. State 0—The MC68340 asserts RMC identify a read-modify-write cycle. The MC68340 places a valid address on A31–A0 and valid function codes on FC3–FC0. The function codes select the address space for the operation. SIZ1/SIZ0 become valid indicate the operand size. The MC68340 drives R/ W high for the read cycle. ...
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... Freescale Semiconductor, Inc. proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample DSACK on the falling edges of the clock until one is recognized. The selected device uses SIZ1/SIZ0, and A0 to latch data from the appropriate section(s) of D15– ...
Page 71
... Freescale Semiconductor, Inc. 3.4.1 Breakpoint Acknowledge Cycle The breakpoint acknowledge cycle allows external hardware to insert an instruction directly into the instruction pipeline as the program executes. The breakpoint acknowledge cycle is generated by the execution of a breakpoint instruction (BKPT) or the assertion of the BKPT pin. The T-bit state (shown in Figure 3-10) differentiates a software breakpoint cycle ( from a hardware breakpoint cycle ( ...
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... Freescale Semiconductor, Inc. 3.4.2 LPSTOP Broadcast Cycle The low power stop (LPSTOP) broadcast cycle is generated by the CPU32 executing the LPSTOP instruction. Since the external bus interface must get a copy of the interrupt mask level from the CPU32, the CPU32 performs a CPU space type 3 write with the mask level encoded on the data bus, as shown in the following figure ...
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... Freescale Semiconductor, Inc. BREAKPOINT OPERATION FLOW PROCESSOR ACKNOWLEDGE BREAKPOINT IF BREAKPOINT INSTRUCTION EXECUTED: 1. SET R/W TO READ 2. SET FUNCTION CODE TO CPU SPACE 3. PLACE CPU SPACE TYPE 0 ON A19–A16 4. PLACE BREAKPOINT NUMBER ON A2–A4 5. CLEAR T-BIT (A1) 6. SET SIZE TO WORD 7. ASSERT AS AND DS IF BKPT PIN ASSERTED: 1 ...
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... Freescale Semiconductor, Inc CLKOUT A31–A20 A19–A16 A4–A1 A15–A5,A0 FC3–FC0 SIZ0 SIZ1 AS DS R/W DSACKx D7–D0 D15–D8 BERR HALT BKPT BREAKPOINT OCCURS Figure 3-12. Breakpoint Acknowledge Cycle Timing (Opcode Returned) MOTOROLA For More Information On This Product BREAKPOINT ENCODING (0000) ...
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... Freescale Semiconductor, Inc CLKOUT A31–A20 A19–A16 A4–A1 A15–A5, A0 FC3–FC0 SIZ0 SIZ1 AS DS R/W DSACKx D7–D0 D15–D8 BERR HALT BKPT BREAKPOINT OCCURS Figure 3-13. Breakpoint Acknowledge Cycle Timing (Exception Signaled) 3-26 For More Information On This Product BREAKPOINT ENCODING (0000) ...
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... Freescale Semiconductor, Inc. 3.4.3 Module Base Address Register Access All internal module registers, including the SIM40, occupy a single 4-Kbyte block that is relocatable along 4-Kbyte boundaries. The location is fixed by writing the desired base address of the SIM40 block to the module base address register using the MOVES instruction. The module base address register is only accessible in CPU space at address $0003FF00. The SFC or DFC register must indicate CPU space (FC3– ...
Page 77
... Freescale Semiconductor, Inc. The interrupt acknowledge cycle is a read cycle. It differs from the read cycle described in 3.3.1 Read Cycle in that it accesses the CPU address space. Specifically, the differences are as follows: 1. FC3–FC0 are set to $7 (FC3/FC2/FC1/FC0 = 0111) for CPU address space. ...
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... Freescale Semiconductor, Inc CLKOUT A31–A4 A3–A1 A0 FC3–FC0 SIZ0 SIZ1 R DSACKx D7–D0 D15–D8 IRQ7–IRQ1 IACK7–IACK1 READ CYCLE *Internal Arbitration may take between 0–2 clock cycles. Figure 3-15. Interrupt Acknowledge Cycle Timing 3.4.4.2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE. When the interrupting device cannot supply a vector number, it requests an automatically generated vector (autovector) ...
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... Freescale Semiconductor, Inc. data will be ignored if AVEC is asserted before or at the same time as the DSACK signals. The vector number supplied in an autovector operation is derived from the interrupt level of the current interrupt. When AVEC is asserted instead of DSACK during an interrupt acknowledge cycle, the MC68340 ignores the state of the data bus and internally generates the vector number (the sum of the interrupt level plus 24 ($18)) ...
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... Freescale Semiconductor, Inc CLKOUT A31–A4 A3–A1 A0 FC3–FC0 SIZ0 SIZ1 R DSACKx D15–D0 AVEC IRQ7–IRQ1 IACK7–IACK1 CYCLE READ * Internal Arbitration may take between 0–2 clocks. Figure 3-16. Autovector Operation Timing MOTOROLA For More Information On This Product 0–2 CLOCKS* ...
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... Freescale Semiconductor, Inc. 3.5 BUS EXCEPTION CONTROL CYCLES The bus architecture requires assertion of DSACK from an external device to signal that a bus cycle is complete. Neither DSACK nor AVEC is asserted in the following cases: • DSACK / AVEC is programmed to respond internally. • The external device does not respond. ...
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... Freescale Semiconductor, Inc. EXAMPLE B: A system uses error detection and correction on RAM contents. The designer may: 1. Delay DSACK until data is verified and assert BERR and HALT simultaneously to indicate to the MC68340 to automatically retry the error cycle (case 5 data is valid, assert DSACK (case 1). ...
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... Freescale Semiconductor, Inc. 3.5.1 Bus Errors BERR can be used to abort the bus cycle and the instruction being executed. BERR takes precedence over DSACK provided it meets the timing constraints described in Section 11 Electrical Characteristics. If BERR does not meet these constraints, it may cause unpredictable operation of the MC68340. If BERR remains asserted into the next bus cycle, it may cause incorrect operation of that cycle ...
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... Freescale Semiconductor, Inc CLKOUT A31–A0 FC3–FC0 R DSACKx D15–D0 BERR READ CYCLE WITH BUS Figure 3-17. Bus Error without DSACK MOTOROLA For More Information On This Product INTERNAL ERROR PROCESSING MC68340 USER’S MANUAL Go to: www.freescale.com STACK WRITE 3- 35 ...
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... Freescale Semiconductor, Inc. S0 CLKOUT A31–A0 FC3–FC0 R DSACKx D15–D0 BERR Figure 3-18. Late Bus Error with DSACK 3.5.2 Retry Operation When both BERR and HALT are asserted by an external device during a bus cycle, the MC68340 enters the retry sequence shown in Figure 3-19. A delayed retry, which is similar to the delayed BERR signal described previously, can also occur (see Figure 3-20) ...
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... Freescale Semiconductor, Inc CLKOUT A31–A0 FC3–FC0 R DSACKx D15–D0 BERR HALT READ CYCLE WITH The MC68340 retries any read or write cycle of a read-modify-write operation separately; RMC remains asserted during the entire retry sequence. Asserting BR along with BERR and HALT provides a relinquish and retry operation. The MC68340 does not relinquish the bus during a read-modify-write operation ...
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... Freescale Semiconductor, Inc. S0 CLKOUT A31–A0 FC3–FC0 R DSACKx D15–D10 BERR HALT Figure 3-20. Late Retry Sequence 3.5.3 Halt Operation When HALT is asserted and BERR is not asserted, the MC68340 halts external bus activity at the next bus cycle boundary (see Figure 3-21). HALT by itself does not terminate a bus cycle ...
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... Freescale Semiconductor, Inc. asserted, the A31–A0, FCx, SIZx, and R/ W signals are again driven to their previous states. The MC68340 does not service interrupt requests while it is halted CLKOUT A31–A0 FC3–FC0 R DSACKx D15–D10 HALT BR BG BGACK READ 3.5.4 Double Bus Fault ...
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... Freescale Semiconductor, Inc. occurs during the stacking operation, the second error is considered a double bus fault. When a double bus fault occurs, the MC68340 halts and asserts HALT. Only a reset operation can restart a halted MC68340. However, bus arbitration can still occur (see 3.6 Bus Arbitration) ...
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... Freescale Semiconductor, Inc. Figure 3- flowchart showing bus arbitration for a single device. This technique allows processing of bus requests during data transfer cycles. Refer to Figures 3-23 and 3-24 for bus arbitration timing diagrams negated at the time that BGACK is asserted. This type of operation applies to a system consisting of the MC68340 and one device capable of bus mastership ...
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... Freescale Semiconductor, Inc. CLKOUT A31–A0 D15– BGACK Figure 3-23. Bus Arbitration Timing Diagram—Idle Bus Case CLKOUT A31–A0 D15– R/W DSACK0, DSACK1 BR BG BGACK Figure 3-24. Bus Arbitration Timing Diagram—Active Bus Case 3-42 For More Information On This Product, ...
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... Freescale Semiconductor, Inc. 3.6.1 Bus Request External devices capable of becoming bus masters request the bus by asserting BR . This signal can be wire-ORed to indicate to the MC68340 that some external device requires control of the bus. The MC68340 is effectively at a lower bus priority level than the external device and relinquishes the bus after it has completed the current bus cycle (if one has started) ...
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... Freescale Semiconductor, Inc. 3.6.4 Bus Arbitration Control The bus arbitration control unit in the MC68340 is implemented with a finite state machine. As discussed previously, all asynchronous inputs to the MC68340 are internally synchronized in a maximum of two cycles of the clock. As shown in Figure 3-25 input signals labeled R and A are internally synchronized versions and BGACK respectively ...
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... Freescale Semiconductor, Inc. RAB STATE BUS REQUEST A - BUS GRANT ACKNOWLEDGE B - BUS CYCLE IN PROGRESS Figure 3-25. Bus Arbitration State Diagram MOTOROLA For More Information On This Product STATE STATE STATE BUS GRANT T - THREE-STATE SIGNAL TO BUS CONTROL V - BUS AVAILABLE TO BUS CONTROL MC68340 USER’S MANUAL Go to: www ...
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... Freescale Semiconductor, Inc. State 0—During state 0, the A31–A0 and FCx become valid driven to indicate a show read or write cycle, and the SIZx pins indicate the number of bytes to transfer. During a read, the addressed peripheral is driving the data bus, and the user must take care to avoid bus conflicts. State 41— ...
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... Freescale Semiconductor, Inc. 3. INTRST (internal reset) goes to all other internal circuits. Synchronous reset sources are not asserted until the end of the current bus cycle, whether or not RMC is asserted. The internal bus monitor is automatically enabled for synchronous resets; therefore, if the current bus cycle does not terminate normally, the bus monitor terminates it ...
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... Freescale Semiconductor, Inc. CLKOUT VCO LOCK V CC 328 TCLKIN RESET BUS CYCLES BUS STATE UNKNOWN NOTES: 1. Internal start-up time. 2. SSP read here read here. 4. First instruction fetched here. Figure 3-28. Power-Up Reset Timing Diagram When a RESET instruction is executed, the MC68340 drives the RESET signal for 512 clock cycles ...
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... Freescale Semiconductor, Inc. SECTION 4 SYSTEM INTEGRATION MODULE The MC68340 system integration module (SIM40) consists of several functions that control the system start-up, initialization, configuration, and the external bus with a minimum of external devices. It also provides the IEEE 1149.1 boundary scan capabilities. The SIM40 includes the following functions: • ...
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... Freescale Semiconductor, Inc. The external bus interface (EBI) handles the transfer of information between the internal CPU32 and memory, peripherals, or other processing elements in the external address space. See Section 3 Bus Operation for further information. The MC68340 dynamically interprets the port size of an addressed device during each bus cycle, allowing operand transfers to or from 8-, 16-, and 32-bit ports ...
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... Freescale Semiconductor, Inc. MC68340 RELOCATABLE MODULE BLOCK MBAR ($0003FF00 FC=0111) RAM (TYPICAL) NOTE: $XXXXX is the value contained in the MBAR bits BA31-BA12. Figure 4-1. SIM40 Module Register Block 4.2.2 System Configuration and Protection Operation The SIM40 allows the user to control certain features of system configuration by writing bits in the module configuration register (MCR) ...
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... Freescale Semiconductor, Inc. Internal Bus Monitor The SIM40 provides an internal bus monitor to monitor the DSACK response time for all internal bus accesses. An option allows the monitoring of external bus accesses. For external bus accesses, four selectable response times are provided to allow for variations in response speed of memory and peripherals used in the system ...
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... Freescale Semiconductor, Inc. CLOCK PRESCALER Figure 4-2. System Configuration and Protection Function 4.2.2.1 SYSTEM CONFIGURATION. Aspects of the system configuration are controlled by the MCR and the autovector register (AVR). The configuration of port B is controlled by the combination of the FIRQ bit in the MCR and the port B pin assignment register (PPARB). Port B pins can function as dedicated I/O lines, chip selects, interrupts, or autovector input ...
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... Freescale Semiconductor, Inc. There are eight arbitration levels for access to the intermodule bus (IMB). The SIM40 is fixed at the highest level (above the programmable level 7), and the CPU32 is fixed at the lowest level (below level 0). The direct memory access (DMA) module is the only other module that can become bus master and arbitrate for the bus ...
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... Freescale Semiconductor, Inc. interrupt (as programmed by the SWRI bit in the SYPCR). The address of the interrupt service routine for the software watchdog interrupt is stored in the software interrupt vector register (SWIV). Figure 4-3 shows a block diagram of the software watchdog as well as the clock control circuits for the periodic interrupt timer. ...
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... Freescale Semiconductor, Inc. 4.2.2.6.1 Periodic Timer Period Calculation. The period of the periodic timer can be calculated using the following equation: periodic interrupt timer period Solving the equation using a crystal frequency of 32.768-kHz with the prescaler disabled gives: periodic interrupt timer period periodic interrupt timer period This gives a range from 122 s, with a PITR value of $01 (00000001 binary ...
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... Freescale Semiconductor, Inc. 4.2.2.6.2 Using the Periodic Timer as a Real-Time Clock. The periodic interrupt timer can be used as a real-time clock interrupt by setting generate an interrupt with a one-second period. Rearranging the periodic timer period equation to solve for the desired count value: PITR count value ...
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... Freescale Semiconductor, Inc. using crystal mode, the system clock frequency is programmable (using the W, X, and Y bits in the SYNCR) over the range specified in Section 11 Electrical Characteristics (see Table 4-2.). EXTAL XTAL CRYSTAL PHASE OSCILLATOR COMPARATOR 64 MODULUS DIVIDER 6 Y NOTE 1: Must be low-leakage capacitor. ...
Page 108
... Freescale Semiconductor, Inc. To use an external clock source (see Figure 4-6), the operating clock frequency can be driven directly into the EXTAL pin (the XTAL pin must be left floating for this case). This approach results in a system clock and CLKOUT that are the same as the input signal frequency, but not tightly coupled to it ...
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... Freescale Semiconductor, Inc. this compare is low-pass filtered and used to control the VCO. The comparator also detects when the external crystal or oscillator stops running to initiate the limp mode for the system clock. The PLL requires an external low-leakage filter capacitor, typically in the range from 0. ...
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... Freescale Semiconductor, Inc. Table 4-2. System Frequencies from 32.768-kHz Reference 000000 131 000101 786 001010 1442 001111 2097 010100 2753 011001 3408 011111 4194 100011 4719 101000 5374 101101 6029 110010 6685 110111 7340 111100 7995 111111 8389 NOTE: System frequencies are in kHz. ...
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... Freescale Semiconductor, Inc. 4.2.4.1 PROGRAMMABLE FEATURES. The chip select function supports the following programmable features: Four Programmable Chip Select Circuits All four chip select circuits are independently programmable from the same list of selectable features. Each chip select circuit has an individual base address register and address mask register that contain the programmed characteristics of that chip select ...
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... Freescale Semiconductor, Inc access matches multiple chip selects, the lowest numbered chip select will have priority. For example, if CS0 and CS2 "overlap" for a certain range, CS0 will assert when accessing the "overlapped" address range, and CS2 will not. Global chip select provides a 16-bit port with three wait states, which allows a boot ROM to be located in any address space and still provide the stack pointer and program counter values at $00000000 and $00000004, respectively ...
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... Freescale Semiconductor, Inc. 4.2.5.2 PORT B. Port B pins can be independently programmed to function as chip selects, IRQ and MODCK pins, or discrete I/O pins. These pins are multiplexed as shown in Figure 4-7. Selection of a pin function is accomplished by a combination of the port B pin assignment register (PPARB) and the FIRQ bit of the MCR. See Table 4-5 for port B combinations ...
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... Freescale Semiconductor, Inc. The number of wait states programmed into the internal wait state generation logic by a chip select can be used even though the pin is not used programmed number of wait states in the CS signal applies to the port B pins configured as IRQ or I/O pins. This is done by programming the chip select with the number of wait states to be added, as though it were to be used ...
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... Freescale Semiconductor, Inc. the MCR disables the software watchdog and periodic interrupt timer, and setting the FRZ0 bit in the MCR disables the bus monitor. 4.3 PROGRAMMING MODEL Figure 4 programming model (register map) of all registers in the SIM40. For more information about a particular register, refer to the description of the module or function indicated in the right column ...
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... Freescale Semiconductor, Inc. ADDR FC 15 000 S MODULE CONFIGURATION REGISTER (MCR) 004 S CLOCK SYNTHESIZER CONTROL REGISTER (SYNCR) 006 S AUTOVECTOR REGISTER (AVR) 010 S/U RESERVED 012 S/U RESERVED 014 S RESERVED 016 S RESERVED 018 S/U RESERVED 01A S/U RESERVED 01C S/U RESERVED 01E S RESERVED ...
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... Freescale Semiconductor, Inc. 4.3.1 Module Base Address Register (MBAR) MBAR BA31 BA30 BA29 BA28 BA27 RESET MBAR BA15 BA14 BA13 BA12 0 RESET BA31–BA12—Base Address Bits 31–12 The base address field is the upper 20 bits of the MBAR that provides for block starting locations in increments of 4-Kbytes. Bits 11, 10— ...
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... Freescale Semiconductor, Inc. An access to this register does not affect external space since the cycle is not run externally. Example code for accessing the MBAR is as follows: Register D0 will contain the value of MBAR. MBAR can be read using the following code: MOVE.L #7,D0 MOVEC.L D0,SFC LEA ...
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... Freescale Semiconductor, Inc. FRZ0—Freeze Bus Monitor Enable 1 = When FREEZE is asserted, the bus monitor is disabled When FREEZE is asserted, the bus monitor continues to operate as programmed. FIRQ—Full Interrupt Request Mode 1 = Configures port B for seven interrupt request lines, autovector, and no external chip selects. ...
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... Freescale Semiconductor, Inc. value of $0 prevents arbitration and causes all SIM40 interrupts, including external interrupts discarded as extraneous. 4.3.2.2 AUTOVECTOR REGISTER (AVR). The AVR contains bits that correspond to external interrupt levels that require an autovector response. Setting a bit allows the SIM40 to assert an internal AVEC during the IACK cycle in response to the specified interrupt request level ...
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... Freescale Semiconductor, Inc. LOC—Loss of Clock Reset 1 = The last reset was caused by a loss of frequency reference to the clock synthesizer. This reset can only occur if the RSTEN bit in the SYNCR is set and the VCO is enabled. SYS—System Reset 1 = The last reset was caused by the CPU32 executing a RESET instruction. The ...
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... Freescale Semiconductor, Inc. SWT1, SWT0—Software Watchdog Timing These bits, along with the SWP bit in the PITR, control the divide ratio used to establish the timeout period for the software watchdog. The software watchdog timeout period is given by the following formula: The software watchdog timeout period, listed in Table 4-7, gives the formula to derive the software watchdog timeout for any clock frequency ...
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... Freescale Semiconductor, Inc. BMT1 4.3.2.6 PERIODIC INTERRUPT CONTROL REGISTER (PICR). The PICR contains the interrupt level and the vector number for the periodic interrupt request. This register can be read or written at any time. Bits 15–11 are unimplemented and always return zero; a write to these bits has no effect. ...
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... Freescale Semiconductor, Inc. PIV7–PIV0—Periodic Interrupt Vector Bits 7–0 These bits contain the value of the vector generated during an IACK cycle in response to an interrupt from the periodic timer. When the SIM40 responds to the IACK cycle, the periodic interrupt vector from the PICR is placed on the bus. This vector number is multiplied by four to form the vector offset, which is added to the vector base register to obtain the address of the vector ...
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... Freescale Semiconductor, Inc. 4.3.2.8 SOFTWARE SERVICE REGISTER (SWSR). The SWSR is the location to which the software watchdog servicing sequence is written. The software watchdog can be enabled or disabled by the SWE bit in the SYPCR. SWSR can be written at any time, but returns all zeros when read. ...
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... Freescale Semiconductor, Inc. SLIMP—Limp Mode loss of input signal reference has been detected, and the VCO is running at approximately one-half the maximum speed (affected by the X-bit ), determined from an internal voltage reference External input signal frequency is at VCO reference. SLOCK—Synthesizer Lock 1 = VCO has locked onto the desired frequency (or system clock is driven externally) ...
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... Freescale Semiconductor, Inc. 4.3.4.1 BASE ADDRESS REGISTERS. There are four 32-bit base address registers in the chip select function, one for each chip select signal. Base Address BA31 BA30 BA29 BA28 BA27 RESET Base Address BA15 BA14 BA13 BA12 BA11 RESET Unaffected by reset BA31– ...
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... Freescale Semiconductor, Inc. NCS—No CPU Space This bit specifies whether or not a chip select will assert on a CPU space access cycle (FC3–FC0 = $7 or $F). If both supervisor data and program accesses are desired, while ignoring CPU space accesses, then this bit should be set. The NCS bit is cleared at reset ...
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... Freescale Semiconductor, Inc. FCM3–FCM0—Function Code Mask Bits 3–0 This field can be used to mask certain function code bits, allowing more than one address space type to be assigned to a chip select. Any set bit masks the corresponding function code bit. DD1, DD0—DSACK Delay Bits 1 and 0 This field determines the number of wait states added before an internal DSACK is returned for that entry ...
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... Freescale Semiconductor, Inc. 4.3.4.3 CHIP SELECT REGISTERS PROGRAMMING EXAMPLE. The following listing is an example of programming a chip select at starting address $00040000, for a block size of 256 Kbytes, accessing supervisor and user data spaces with a 16-bit port requiring two wait states. There will be no write protection, no fast termination, and no CPU space accesses ...
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... Freescale Semiconductor, Inc. 4.3.5.2 PORT A PIN ASSIGNMENT REGISTER 2 (PPARA2). PPARA2 selects between an address and IACK function for the port A pins. Any set bit defines the corresponding pin IACK output pin. Any cleared bit defines the corresponding pin address bit as defined in the register diagram. Any set bits in PPARA1 override the configuration set in PPARA2 ...
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... Freescale Semiconductor, Inc. 4.3.5.5 PORT B PIN ASSIGNMENT REGISTER (PPARB). PPARB controls the function of each port B pin. Any set bit defines the corresponding pin IRQ input defined in Table 4-5. Any cleared bit defines the corresponding pin discrete I/O pin ( the FIRQ bit of the MCR is zero) controlled by the port B data and data direction registers. The MODCK signal has no function after reset. PPARB is configured to all ones at reset to provide for MODCK, IRQ7 , IRQ6 , IRQ5 , IRQ3 , and CS3 – ...
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... Freescale Semiconductor, Inc. 4.4 MC68340 INITIALIZATION SEQUENCE The following paragraphs discuss a suggested method for initializing the MC68340 after power-up. 4.4.1 Startup RESET is asserted by the MC68340 during the time in which V is locking onto the frequency, and the MC68340 is going through the reset operation. After ...
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... Freescale Semiconductor, Inc. System Protection Control Register (SYPCR) (Note that this register can only be written once after reset.) • Enable the software watchdog, if desired (SWE bit). • If the watchdog is enabled, select whether a system reset or a level 7 interrupt is desired at timeout (SWRI bit). ...
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... Freescale Semiconductor, Inc. 4.4.3 SIM40 Example Configuration Code The following code is an example configuration sequence for the SIM40 module. *************************************************************************** * MC68340 basic SIM40 register initialization example code: * This code is used to initialize the MC68340's internal SIM40 registers, * providing basic functions for operation includes chip select programming for external devices. ...
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... Freescale Semiconductor, Inc. *************************************************************************** * Initialization code *************************************************************************** * Start Chip Select Initialization: INIT340 MOVE.W #$2700,SR *************************************************************************** * Set up default module base address value MOVEQ.L #7,D0 MOVEC.L D0,DFC MOVE.L #MODBASE+1,D0 MOVES.L D0,MBAR *************************************************************************** * Set up system protection register: * Software watchdog disabled, double bus fault monitor disabled, bus * monitor BERR after 16 clocks. ...
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... Freescale Semiconductor, Inc. *************************************************************************** * Data table for chip select initialization *************************************************************************** * CS0 - EPROM - 00060000-0007ffff, 3-wait states, 16-bit term., write protect CSAM0$ DC.L $0001FFFD CSBAR0$ DC.L $00060009 * CS1 - RAM - 00000000-0000ffff, fast termination CSAM1$ DC.L $0000FFF0 CSBAR1$ DC.L $00000005 * CS2 - external device - 00FFE8xx, external termination CSAM2$ DC ...
Page 138
... Freescale Semiconductor, Inc. SECTION 5 CPU32 The CPU32, the first-generation instruction processing module of the M68300 family, is based on the industry-standard MC68000 core processor. It has many features of the MC68010 and MC68020 as well as unique features suited for high-performance processor applications. The CPU32 provides a significant performance increase over the MC68000 CPU, yet maintains source-code and binary-code compatibility with the M68000 family ...
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... Freescale Semiconductor, Inc. 5.1.1 Features Features of the CPU32 are as follows: • Fully Upward Object-Code Compatible with M68000 Family • Virtual Memory Implementation • Loop Mode of Instruction Execution • Fast Multiply, Divide, and Shift Instructions • Fast Bus Interface with Dynamic Bus Port Sizing • ...
Page 140
... Freescale Semiconductor, Inc. CPU32 uses instruction restart, which requires that only a small portion of the internal machine state be saved. After correcting the page fault, the machine state is restored, and the instruction is refetched and restarted. This process is completely transparent to the application program. SEQUENCER ...
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... Freescale Semiconductor, Inc. condition and count are checked after each execution of the data operations of the looped instruction. The CPU32 automatically exits the loop mode on interrupts or other exceptions. 5.1.4 Vector Base Register The vector base register (VBR) contains the base address of the 1024-byte exception vector table, which consists of 256 exception vectors ...
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... Freescale Semiconductor, Inc. 5.1.6 Addressing Modes Addressing in the CPU32 is register oriented. Most instructions allow the results of the specified operation to be placed either in a register or directly in memory; this flexibility eliminates the need for extra instructions to store register contents in memory. The seven basic addressing modes are as follows: • ...
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... Freescale Semiconductor, Inc. Mnemonic Description ABCD Add Decimal with Extend ADD Add ADDA Add Address ADDI Add Immediate ADDQ Add Quick AND Logical AND ANDI Logical AND Immediate ASL Arithmetic Shift Left ASR Arithmetic Shift Right Bcc Branch Conditionally (16 Tests) BCHG ...
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... Freescale Semiconductor, Inc. 5.1.7.1 TABLE LOOKUP AND INTERPOLATE INSTRUCTIONS. To maximize throughput for real-time applications, reference data is often “particulated” and stored in memory for quick access. The storage of each data point would require an inordinate amount of memory. The table instruction requires only a sample of data points stored in the array, thus reducing memory requirements ...
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... Freescale Semiconductor, Inc. 5.2 ARCHITECTURE SUMMARY The CPU32 is upward source- and object-code compatible with the MC68000 and MC68010 downward source- and object-code compatible with the MC68020. Within the M68000 family, architectural differences are limited to the supervisory operating state. User state programs can be executed unchanged on upward-compatible devices. ...
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... Freescale Semiconductor, Inc Figure 5-3. User Programming Model Figure 5-4. Supervisor Programming Model Supplement MOTOROLA For More Information On This Product (USP CCR 15 0 A7' (SSP (CCR SFC DFC MC68340 USER’S MANUAL Go to: www.freescale.com DATA REGISTERS ADDRESS REGISTERS USER STACK POINTER PROGRAM COUNTER ...
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... Freescale Semiconductor, Inc. 5.2.2 Registers Registers D7–D0 are used as data registers for bit, byte (8-bit), word (16-bit), long-word (32-bit), and quad-word (64-bit) operations. Registers and the USP and SSP are address registers that may be used as software SPs or base address registers. Register A7 (shown as A7 and A7' in Figures 5-3 and 5- register designation that applies to the USP in the user privilege level and to the SSP in the supervisor privilege level ...
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... Freescale Semiconductor, Inc. 5.3 INSTRUCTION SET The following paragaphs describe the set of instructions provided in the CPU32 and demonstrate their use. Descriptions of the instruction format and the operands used by instructions are included. After a summary of the instructions by category, a detailed description of each instruction is listed in alphabetical order. Complete programming information is provided, as well as a description of condition code computation and an instruction format summary ...
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... Freescale Semiconductor, Inc. 5.3.1.1.2 Table Lookup and Interpolation (TBL). To maximize throughput for real-time applications, reference data is often precalculated and stored in memory for quick access. The storage of sufficient data points can require an inordinate amount of memory. The TBL instruction uses linear interpolation to recover intermediate values from a sample of data points, and thus conserves memory ...
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... Freescale Semiconductor, Inc. Besides the operation code, which specifies the function to be performed, an instruction defines the location of every operand for the function. Instructions specify an operand location in one of three ways: • Register Specification • Effective Address • Implicit Reference The register field within an instruction specifies the register to be used. Other fields within the instruction specify whether the register is an address or data register and how used. The M68000PM/AD, M68000 Family Programmer’ ...
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... Freescale Semiconductor, Inc. (...) Contents of a referenced location Example: (Rn) refers to the contents of Rn CCR Condition code register (lower byte of SR) X—extend bit N—negative bit Z—zero bit V—overflow bit C—carry bit PC Program counter SP Active stack pointer SR Status register SSP Supervisor stack pointer USP ...
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... Freescale Semiconductor, Inc. 5.3.3 Instruction Summary The instructions form a set of tools to perform the following operations: Data movement Bit manipulation Integer arithmetic Binary-coded decimal arithmetic Logic Program control Shift and rotate System control The complete range of instruction capabilities combined with the addressing modes described previously provide flexibility for program development ...
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... Freescale Semiconductor, Inc. Table 5-2. Instruction Set Summary Opcode ABCD Source 10 + Destination ADD Source + Destination ADDA Source + Destination ADDI Immediate Data + Destination ADDQ Immediate Data + Destination ADDX Source + Destination + X AND Source Destination ANDI Immediate Data ANDI to CCR Source CCR ANDI to SR ...
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... Freescale Semiconductor, Inc. Table 5-2. Instruction Set Summary (Continued) Opcode CMP2 Compare Rn < lower-bound or Rn > upper-bound and Set Condition Codes DBcc If condition false then (Dn – –1 then DIVS Destination/Source DIVSL DIVU Destination/Source DIVUL EOR Source Destination EORI Immediate Data EORI Source ...
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... Freescale Semiconductor, Inc. Table 5-2. Instruction Set Summary (Continued) Opcode MOVE to CCR Source CCR MOVE from SR If supervisor state then SR Destination else TRAP MOVE supervisor state then Source else TRAP MOVE USP If supervisor state then USP else TRAP MOVEC If supervisor state ...
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... Freescale Semiconductor, Inc. Table 5-2. Instruction Set Summary (Concluded) Opcode ROXL,ROXR Destination Rotated with X by count RTD (SP) PC RTE If supervisor state the (SP) SR SP; restore state and deallocate stack according to (SP) else TRAP RTR (SP) CCR (SP) PC RTS (SP) PC SBCD Destination 10 – Source 10 – X ...
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... Freescale Semiconductor, Inc. 5.3.3.1 CONDITION CODE REGISTER. The CCR portion of the SR contains five bits that indicate the result of a processor operation. Table 5-3 lists the effect of each instruction on these bits. The carry bit and the multiprecision extend bit are separate in the M68000 Family to simplify programming techniques that use them ...
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... Freescale Semiconductor, Inc. Table 5-3. Condition Code Computations (Continued) Operations X ROR — ROR ( — NOTE : The following notations apply to this table only. — = Not affected U = Undefined ? = See special definition = General case ... R0 Boolean AND V = Boolean OR 5.3.3.2 DATA MOVEMENT INSTRUCTIONS. The MOVE instruction is the basic means of transferring and storing address and data ...
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... Freescale Semiconductor, Inc. 5.3.3.3 INTEGER ARITHMETIC OPERATIONS. The arithmetic operations include the four basic operations of add (ADD), subtract (SUB), multiply (MUL), and divide (DIV) as well as arithmetic compare (CMP, CMPM, CMP2), clear (CLR), and negate (NEG). The instruction set includes ADD, CMP, and SUB instructions for both address and data operations with all operand sizes valid for data operations ...
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... Freescale Semiconductor, Inc. Table 5-5. Integer Arithmetic Operations Operand Instruction Syntax ADD Dn ADDA ADDI # data ea ADDQ # data ea ADDX Dn, Dn – (An), – (An) CLR ea CMP CMPA CMPI # data ea CMPM (An) +, (An) + CMP2 DIVS/DIVU Dr: DIVSL/DIVUL ea , Dr:Dq EXT Dn Dn EXTB Dn MULS/MULU Dh:Dl NEG ea NEGX ea SUB Dn, ea ...
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... Freescale Semiconductor, Inc. 5.3.3.4 LOGIC INSTRUCTIONS. The logical operation instructions (AND, OR, EOR, and NOT) perform logical operations with all sizes of integer data operands. A similar set of immediate instructions (ANDI, ORI, and EORI) provide these logical operations with all sizes of immediate data. The test (TST) instruction arithmetically compares the operand with zero, placing the result in the CCR ...
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... Freescale Semiconductor, Inc. Table 5-7. Shift and Rotate Operations Operand Instruction Syntax ASL Dn data Dn ea ASR Dn data Dn ea LSL Dn data Dn ea LSR Dn data Dn ea ROL Dn data Dn ea ROR Dn data Dn ea ROXL Dn data Dn ea ROXR Dn data Dn ea SWAP Dn 5.3.3.6 BIT MANIPULATION INSTRUCTIONS. Bit manipulation operations are accomplished using the following instructions: bit test (BTST), bit test and set (BSET), bit test and clear (BCLR), and bit test and change (BCHG) ...
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... Freescale Semiconductor, Inc. 5.3.3.7 BINARY-CODED DECIMAL (BCD) INSTRUCTIONS. Five instructions support operations on BCD numbers. The arithmetic operations on packed BCD numbers are add decimal with extend (ABCD), subtract decimal with extend (SBCD), and negate decimal with extend (NBCD). Table 5 summary of the BCD operations. ...
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... Freescale Semiconductor, Inc. To specify conditions for change in program control, condition codes must be substituted for the letters "cc" in conditional program control opcodes. Condition test mnemonics are given below. Refer to 5.3.3.10 Condition Tests for detailed information on condition codes. CC — Carry clear CS — Carry set EQ — ...
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... Freescale Semiconductor, Inc. Table 5-11. System Control Operations Operand Instruction Syntax ANDI # data , SR EORI # data , SR MOVE SR, ea MOVEA USP, An An, USP MOVEC Rc, Rn Rn, Rc MOVES Rn ORI # data , SR RESET none RTE none STOP # data LPSTOP # data BKPT # data BGND none CHK CHK2 ...
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... Freescale Semiconductor, Inc. 5.3.3.10 CONDITION TESTS. Conditional program control instructions and the TRAPcc instruction execute on the basis of condition tests. A condition test is the evaluation of a logical expression related to the state of the CCR bits. If the result is 1, the condition is true. If the result is 0, the condition is false. For example, the T condition is always true, and the EQ condition is true only if the Z-bit condition code is true ...
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... Freescale Semiconductor, Inc. Two additional examples show how TBLSN can reduce cumulative error when multiple table lookup and interpolation operations are used in a calculation. Example 4 demonstrates addition of the results of three table interpolations. Example 5 illustrates use of TBLSN in surface interpolation. 5.3.4.1 TABLE EXAMPLE 1: STANDARD USAGE. The table consists of 257 word entries ...
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... Freescale Semiconductor, Inc. The table instruction is executed with the following bit pattern in Dx: 31 NOT USED Table Entry Offset Interpolation Fraction Using this information, the table instruction calculates dependent variable 1669 + (128 (1679 – 1669)) / 256 = 1674 5.3.4.2 TABLE EXAMPLE 2: COMPRESSED TABLE. In Example 2 (see Figure 5-8), the data from Example 1 has been compressed by limiting the maximum value of the independent variable ...
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... Freescale Semiconductor, Inc. Table 5-14. Compressed Table Entries Entry Number 2 3 Since the table is reduced from 257 to 5 entries, independent variable X must be scaled appropriately. In this case the scaling factor is 64, and the scaling is done by a single instruction: Thus, Dx now contains the following bit pattern: ...
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... Freescale Semiconductor, Inc. Y 1024 (Subroutine) The first column is the value passed to the subroutine, the second column is the value expected by the table instruction, and the third column is the result returned by the subroutine. MOTOROLA For More Information On This Product, 2048 3072 X INDEPENDENT VARIABLE Figure 5-9 ...
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... Freescale Semiconductor, Inc. The following value has been calculated for independent variable X: 31 NOT USED Since 8-bit value, the upper four bits are used as a table offset and the lower four bits are used as an interpolation fraction. The following results are obtained from the ...
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... Freescale Semiconductor, Inc. First, the results of each TBL are rounded with the TBLS round-to-nearest-even algorithm. The following values would be returned by TBLS: Summing, the following result is obtained: Now, using the same TBL results, the sum is first calculated and then rounded according to the same algorithm: Rounding yields: The second result is preferred ...
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... Freescale Semiconductor, Inc. 5.3.4.5 Table Example 5: Surface Interpolations. The various forms of table can be used to perform surface (3D) TBLs. However, since the calculation must be split into a series of 2D TBLs, the possibility of losing precision in the intermediate results is possible. The following code sequence, incorporating both TBLS and TBLSN, eliminates this possibility ...
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... Freescale Semiconductor, Inc. 5.4.1 State Transitions The processor is in normal, background, or exception state unless halted. When the processor fetches instructions and operands or executes instructions the normal processing state. The stopped condition, which the processor enters when a STOP or LPSTOP instruction is executed variation of the normal state in which no further bus cycles are generated ...
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... Freescale Semiconductor, Inc. All exception processing is performed at the supervisor level. All bus cycles generated during exception processing are supervisor references, and all stack accesses use the SSP. Instructions that have important system effects can only be executed at supervisor level. For instance, user programs are not permitted to execute STOP, LPSTOP, or RESET instructions ...
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... Freescale Semiconductor, Inc. 5.5.1 Exception Vectors An exception vector is the address of a routine that handles an exception. The VBR contains the base address of a 1024-byte exception vector table, which consists of 256 exception vectors. Sixty-four vectors are defined by the processor, and 192 vectors are reserved for user definition as interrupt vectors ...
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... Freescale Semiconductor, Inc. Because there is no protection on the 64 processor-defined vectors, external devices can access vectors reserved for internal purposes. This practice is strongly discouraged. All exception vectors, except the reset vector, are located in supervisor data space. The reset vector is located in supervisor program space. Only the initial reset vector is fixed in the processor memory map ...
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... Freescale Semiconductor, Inc. Finally, the processor prepares to resume normal execution of instructions. The exception vector offset is determined by multiplying the vector number by 4, and the offset is added to the contents of the VBR to determine displacement into the exception vector table. The exception vector is loaded into the PC other exception is pending, the processor will resume normal execution at the new address in the PC ...
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... Freescale Semiconductor, Inc. When the CPU32 completes exception processing ready to begin either exception processing for a pending exception or execution of a handler routine. Priority assignment governs the order in which exception processing occurs, not the order in which exception handlers are executed. Table 5-17. Exception Priority Groups ...
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... Freescale Semiconductor, Inc. 5.5.2 Processing of Specific Exceptions The following paragraphs provide details concerning sources of specific exceptions, how each arises, and how each is processed. 5.5.2.1 RESET. Assertion of RESET by external hardware or assertion of the internal RESET signal by an internal module causes a reset exception. The reset exception has the highest priority of any exception ...
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... Freescale Semiconductor, Inc FETCH VECTOR # 0 OTHERWISE SP (VECTOR # 0) FETCH VECTOR # 1 OTHERWISE PC PREFETCH 3 WORDS OTHERWISE BEGIN INSTRUCTION EXECUTION Figure 5-11. Reset Operation Flowchart 5-44 For More Information On This Product, ENTRY T0,T1 I2:I0 VBR . BUS ERROR BUS ERROR (VECTOR # 1) BUS ERROR/ ADDRESS ERROR (DOUBLE BUS FAULT) ...
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... Freescale Semiconductor, Inc. 5.5.2.2 BUS ERROR. A bus error exception occurs when an assertion of the BERR signal is acknowledged. The BERR signal can be asserted by one of three sources: 1. External logic by assertion of the BERR input pin 2. Direct assertion of the internal BERR signal by an internal module 3. Direct assertion of the internal BERR signal by the on-chip hardware watchdog ...
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... Freescale Semiconductor, Inc. case of a released operand write. Released write exceptions are delayed until the next instruction boundary or attempted operand access. An address exception on a branch to an odd address is delayed until the PC is changed. No exception occurs if the branch is not taken. In this case, the fault address and return PC value placed in the exception stack frame are the odd address, and the current instruction PC points to the instruction that caused the exception ...
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... Freescale Semiconductor, Inc. 5.5.2.6 HARDWARE BREAKPOINTS. The CPU32 recognizes hardware breakpoint requests. Hardware breakpoint requests do not force immediate exception processing, but are left pending. An instruction breakpoint is not made pending until the instruction corresponding to the request is executed. A pending breakpoint can be acknowledged between instructions or at the end of exception processing ...
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... Freescale Semiconductor, Inc. All unimplemented instructions are reserved for use by Motorola for enhancements and extensions to the basic M68000 architecture. Opcode pattern $4AFC is defined to be illegal on all M68000 family members. Those customers requiring the use of an unimplemented opcode for synthesis of "custom instructions," operating system calls, etc., should use this opcode ...
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... Freescale Semiconductor, Inc. 5.5.2.10 TRACING. To aid in program development, M68000 processors include a facility to allow tracing of instruction execution. CPU32 tracing also has the ability to trap on changes in program flow. In trace mode, a trace exception is generated after each instruction executes, allowing a debugging program to monitor the execution of a program under test ...
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... Freescale Semiconductor, Inc instruction is executed and an interrupt is pending on completion, the trace exception is processed before the interrupt exception instruction forces an exception, the forced exception is processed before the trace exception instruction is executed and a breakpoint is pending upon completion of the instruction, the trace exception is processed before the breakpoint. ...
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... Freescale Semiconductor, Inc. tracing. Priority level is then set to the level of the interrupt, and the processor fetches a vector number from the interrupting device (CPU space $F). The fetch bus cycle is classified as an interrupt acknowledge, and the encoded level number of the interrupt is placed on the address bus. ...
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... Freescale Semiconductor, Inc. attempting to read the stack frame. The version number is located in the most significant byte (bits 15–8) of the internal register word at location SP validity check ensures that stack frame data will be properly interpreted in multiprocessor systems frame is invalid, a format error exception is taken inaccessible, a bus error exception is taken ...
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... Freescale Semiconductor, Inc. The TP field defines the class of the faulted bus operation. Two bus error exception frame types are defined. One is for faults on prefetch and operand accesses, and the other is for faults during exception frame stacking Operand or prefetch bus fault 1 = Exception processing bus fault MV is set when the operand transfer portion of the MOVEM instruction is in progress at the time of a bus fault ...
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... Freescale Semiconductor, Inc. Read and write bus cycles are distinguished by the RW bit. Read bus cycles will set this bit, and write bus cycles will clear it reloaded into the bus controller if the RR bit is set during unstacking Faulted cycle was an operand write 1 = Faulted cycle was a prefetch or operand read The LG bit indicates an original operand size of long word cleared if the original operand was a byte or word— ...
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... Freescale Semiconductor, Inc. The SSW for a released write fault contains the following bit pattern TR, B1, and B0 are set if the corresponding exception is pending when the bus error exception is taken. Status regarding the faulted bus cycle is reflected in the LG, SIZ, and FUNC fields. The remainder of the stack contains the PC of the next unexecuted instruction, the current SR, the address of the faulted memory location, and the contents of the data buffer that was to be written to memory ...
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... Freescale Semiconductor, Inc. 5.5.3.1.3 Type III—Faults During MOVEM Operand Transfer. Bus faults that occur as a result of MOVEM operand transfer are classified as type III faults. MOVEM instruction prefetch faults are type II faults. Type III faults cause an immediate exception that aborts the current instruction. None of the registers altered during execution of the faulted instruction are restored prior to execution of the fault handler ...
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... Freescale Semiconductor, Inc. exception is also stacked. This data is placed on the stack in the format shown in Figure 5-13. The return address from the initial exception is stacked for RTE . 5.5.3.2 CORRECTING A FAULT. There are two ways to complete a faulted released write bus cycle. The first is to use a software handler. The second is to rerun the bus cycle via RTE ...
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... Freescale Semiconductor, Inc. 5.5.3.2.3 Type II—Correcting Faults via RTE. Instructions aborted because of a type II fault are restarted upon return from the exception handler. A fault handler must establish safe restart conditions fault is caused by a nonresident page in a demand-paged virtual memory configuration, the fault address must be read from the stack, and the appropriate page retrieved ...
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... Freescale Semiconductor, Inc. exceptions, will be restarted upon return from the exception handler. When a fault occurs after an operand has transferred, that transfer is not "undone". However, these memory locations are accessed a second time when the instruction is restarted register used calculation is overwritten before a fault occurs, an incorrect EA is calculated upon instruction restart. 5.5.3.2.6 Type III— ...
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... Freescale Semiconductor, Inc. 5.5.4 CPU32 Stack Frames The CPU32 generates three different stack frames: four-word frames, six-word frames, and twelve-word bus error frames. 5.5.4.1 FOUR-WORD STACK FRAME. This stack frame is created by interrupt, format error, TRAP #n, illegal instruction, A-line and F-line emulator trap, and privilege violation exceptions ...
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... Freescale Semiconductor, Inc. Bus operation in progress at the time of a fault is conveyed by the SSW The bus error stack frame is 12 words in length. There are three variations of the frame, each distinguished by different values in the SSW TP and MV fields. An internal transfer count register appears at location SP + $14 in all bus error stack frames ...
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... Freescale Semiconductor, Inc +$02 +$ +$08 +$0C +$10 +$14 +$ Figure 5-15. Format $C—BERR Stack for Prefetches and Operands 15 SP +$02 +$ +$08 +$0C +$10 +$14 +$ Figure 5-16. Format $C—BERR Stack on MOVEM Operand 5-62 For More Information On This Product, STATUS REGISTER RETURN PROGRAM COUNTER HIGH RETURN PROGRAM COUNTER LOW 0 VECTOR OFFSET ...
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... Freescale Semiconductor, Inc +$02 +$ +$08 +$0C +$10 FAULTED INSTRUCTION PROGRAM COUNTER HIGH (SIX WORD FRAME ONLY) FAULTED INSTRUCTION PROGRAM COUNTER LOW (SIX WORD FRAME ONLY) +$14 +$ Figure 5-17. Format $C—Four- and Six-Word BERR Stack 5.6 DEVELOPMENT SUPPORT All M68000 family members have the following special features that facilitate applications development. Trace on Instruction Execution— ...