MPC850DEVR50BU Freescale Semiconductor, MPC850DEVR50BU Datasheet

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... RISC communications processor (referred to as the CP). This separate processor off-loads peripheral tasks from the embedded MPC8xx core. © Freescale Semiconductor, Inc., 2005. All rights reserved. Document Number: MPC850EC Rev. 2, 07/2005 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 ...

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... Additional documentation may be provided for parts listed in MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev Table 1. MPC850 Functionality Matrix Ethernet ATM Support USB Support Support Yes - Yes Yes - Yes Yes Yes Yes Yes Yes Yes Table Multi-channel Number of HDLC PCMCIA Slots Support Supported - Yes Freescale Semiconductor ...

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... Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs) — Performs branch folding and branch prediction with conditional prefetch, but without conditional execution MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 2-Kbyte I-Cache Instruction MMU ...

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... Selectable write protection — On-chip bus arbiter supports one external bus master — Special features for burst mode support • General-purpose timers — Four 16-bit timers or two 32-bit timers MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... Synchronous UART — Serial infrared (IrDA) — Totally transparent (bit streams) — Totally transparent (frame based with optional cyclic redundancy check (CRC)) MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor stops transmission GRACEFUL STOP TRANSMIT Features CLOSE RXBD ...

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... Sleep: all units disabled except real-time clock and periodic interrupt timer. PLL is active for fast wake-up — Deep sleep: all units disabled including PLL, except the real-time clock and periodic interrupt timer — Low-power stop: to provide lower power dissipation MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or V the package thermal characteristics for the MPC850. MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 2. Maximum Ratings Symbol VDDH -0 ...

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... TBD 50 TBD Table 5. DC Electrical Specifications Symbol VDDH, VDDL, KAPWR, VDDSYN VDDH, VDDL, KAPWR, VDDSYN VIH VIH Value Unit 2 °C °C °C/W 24 °C Maximum Unit 515 mW 590 mW 725 mW Min Max Unit 3.0 3.6 3.135 3.465 2.0 3.6 2.0 5.5 Freescale Semiconductor ...

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... IBIS model at any output voltage level. 5 Power Considerations The average chip-junction temperature θ )(1) • where ° Ambient temperature , A MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Symbol VIL VIHC VOH VOL in °C can be obtained from the equation Power Considerations Min ...

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... MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev °C/W junction to ambient , , P and can be neglected • INT is Using this value of K the values power supply should be bypassed to ground using at least four CC and GND should be kept to less than half neglected an approximate , I/O and T can be obtained and GND CC Freescale Semiconductor ...

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... CLKOUT to TSIZ[0–1], REG, RSV, AT[0–3] BDIP, PTR valid B8b CLKOUT to BR, BG, VFLS[0–1], VF[0–2], IWP[0–2], FRZ, LWP[0–1], STS valid MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 6. Bus Operation Timing 50 MHz 66 MHz Min Max Min ...

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... Freescale Semiconductor Unit — ...

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... WE[0–3] negated GPCM write access TRLX = 0,1 CSNT = 1, EBDF = 0 B28b CLKOUT falling edge to CS negated GPCM write access TRLX = 0,1 CSNT = 1, ACS = 10 or ACS = 11, EBDF = 0 MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 1 (continued) 50 MHz 66 MHz 80 MHz Min Max Min ...

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... Cap Load FFACT (default Unit Max 50 pF) 16.00 0.375 50.00 ns 16.00 0.375 50.00 ns — 0.250 50.00 ns — 0.500 50.00 ns — 0.250 50.00 ns — 0.500 50.00 ns — 1.500 50.00 ns — 1.500 50.00 ns — 0.375 50.00 ns — 0.375 50.00 ns Freescale Semiconductor ...

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... WE[0–3] negated to A[6–31] invalid GPCM write access TRLX = 1, CSNT =1, CS negated to A[6–31] invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10 or ACS = 11, EBDF = 1 MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 1 (continued) 50 MHz 66 MHz 80 MHz Min Max ...

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... Cap Load FFACT (default Unit Max 50 pF) 6.00 — 50.00 ns 13.00 0.250 50.00 ns 8.00 — 50.00 ns 13.00 0.250 50.00 ns 0.375 50.00 ns 6.00 — 50.00 ns 13.00 0.250 50.00 ns 8.00 — 50.00 ns 13.00 0.250 50.00 ns 0.375 50.00 ns 6.00 — 50.00 ns Freescale Semiconductor ...

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... AS valid to CLKOUT rising edge 11 B40 A[6–31], TSIZ[0–1], RD/WR, BURST, valid to CLKOUT rising edge. B41 TS valid to CLKOUT rising edge (setup time) MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 1 (continued) 50 MHz 66 MHz 80 MHz Min Max Min Max Min 5 ...

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... MHz 66 MHz Min Max Min Max 2.00 — 2.00 — — TBD — TBD - 20 x FFACTOR) -20 x FFACTOR) 1ns(CAP LOAD - 50 (continued) 80 MHz Cap Load FFACT (default Min Max 50 pF) 2.00 — — 50.00 TBD — — 50.00 Freescale Semiconductor Unit ns ns ...

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... B Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification Figure 3 provides the timing for the external clock. CLKOUT MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 0 2.0 V 2.0 V 0 ...

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... CLKOUT TS, BB TA, BI TEA Figure 5. Synchronous Active Pullup and Open-Drain Outputs Signals Timing MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev B8a B9 B8b B11 B12 B12a B11a B14 B15 B13 B13a Freescale Semiconductor ...

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... TEA, KR, RETRY BB, BG, BR Figure 6. Synchronous Input Signals Timing Figure 7 provides normal case timing for input data. CLKOUT TA D[0:31], DP[0:3] MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor B16 B17 B16a B17a B16b B17 B16 B17 B18 B19 Figure 7. Input Data Timing in Normal Case ...

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... GPCM factors. CLKOUT TS A[6:31] CSx OE WE[0:3] D[0:31], DP[0:3] Figure 9. External Bus Read Timing (GPCM Controlled—ACS = 00) MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev B20 B21 B11 B12 B8 B22 B25 B28 B18 B23 B26 B19 Freescale Semiconductor ...

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... Figure 10. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT TS A[6:31] CSx OE D[0:31], DP[0:3] Figure 11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor B11 B12 B8 B22a B24 B25 B18 B11 B12 ...

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... Bus Signal Timing CLKOUT B11 TS A[6:31] CSx OE D[0:31], DP[0:3] Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11) MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev B12 B8 B22a B27 B27a B22bB22c B18 B23 B26 B19 Freescale Semiconductor ...

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... GPCM factors. CLKOUT TS A[6:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 13. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0) MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor B11 B12 B8 B22 B25 B26 B8 Bus Signal Timing B30 B23 B28 ...

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... Bus Signal Timing CLKOUT TS A[6:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1) MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev B11 B12 B8 B22 B28bB28d B25 B26 B28a B28c B8 B30aB30c B23 B29c B29g B29a B29f B9 Freescale Semiconductor ...

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... CLKOUT B11 TS A[6:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1) MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor B12 B8 B22 B28b B28d B25 B26 B8 B28a B28c Bus Signal Timing B30b B30d B23 ...

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... BS_B[0:3] GPL_A[0–5], GPL_B[0–5] Figure 16. External Bus Timing (UPM Controlled Signals) MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev B31a B31d B31 B34 B34a B34b B32aB32d B32 B35 B36 B35a B35b B33 B31c B31b B32c B32b B33a Freescale Semiconductor ...

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... UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT CSx BS_A[0:3], BS_B[0:3] GPL_A[0–5], GPL_B[0–5] Figure 18. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor B38 B38 Bus Signal Timing 29 ...

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... AS CSx, WE[0:3], OE, GPLx, BS[0:3] Figure 21. Asynchronous External Master—Control Signals Negation Timing MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev B41 B42 B40 B39 B40 B43 B22 B22 Freescale Semiconductor ...

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... Figure 22. Interrupt Detection Timing for External Level Sensitive Lines Figure 23 provides the interrupt detection timing for the external edge-sensitive lines. CLKOUT IRQx Figure 23. Interrupt Detection Timing for External Edge Sensitive Lines MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 7. Interrupt Timing 50 MHz 1 Min Max Min 6.00 — ...

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... Freescale Semiconductor ...

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... PCMCIA access cycle timing for the external bus read. CLKOUT TS A[6:31] REG CE1/CE2 PCOE, IORD ALE D[0:31] Figure 24. PCMCIA Access Cycles Timing External Bus Read MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor P44 P46 P45 P48 P50 P52 P53 B18 Bus Signal Timing P47 ...

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... Figure 26 provides the PCMCIA WAIT signals detection timing. CLKOUT WAIT_B Figure 26. PCMCIA WAIT Signal Detection Timing MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev P44 P46 P45 P48 P50 P52 P53 B8 P55 P56 P47 P49 P51 P54 P52 B9 Freescale Semiconductor ...

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... Output Signals HRESET OP2, OP3 Figure 28 provides the PCMCIA output port timing for the MPC850. CLKOUT Input Signals MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 9. PCMCIA Port Timing 50 MHz Min Max — 19.00 1 18.00 — 5.00 — ...

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... Figure 30. Debug Port Timings 66 MHz 80 MHz Unit Min Max Min Max 91.00 — 75.00 — ns 38.00 — 31.00 — ns 0.00 3.00 0.00 3.00 ns 8.00 — 8.00 — ns 5.00 — 5.00 — ns 0.00 15.00 0.00 15.00 ns 0.00 2.00 0.00 2.00 ns D62 D63 Freescale Semiconductor ...

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... DSDI, DSCK set up R80 R81 DSDI, DSCK hold time SRESET negated to CLKOUT rising R82 edge for DSDI and DSCK sample MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 11. Reset Timing 50 MHz 66MHz Min Max Min Max — ...

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... CLKOUT HRESET RSTCONF D[0:31] (OUT) (Weak) Figure 32. Reset Timing—Data Bus Weak Drive during Configuration MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev R71 R76 R73 R74 R75 R69 R79 R77 R78 Freescale Semiconductor ...

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... J94 TCK falling edge to output high impedance Boundary scan input valid to TCK rising edge J95 J96 TCK rising edge to boundary scan input invalid MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor R70 R82 R80 R80 R81 Figure 34 Table 12. JTAG Timing ...

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... Figure 35. JTAG Test Access Port Timing Diagram TCK TRST MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev J82 J83 J82 J84 Figure 34. JTAG Test Clock Input Timing J85 J86 J87 J88 J91 J90 Figure 36. JTAG TRST Timing Diagram J83 J84 J89 Freescale Semiconductor ...

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... Data-in setup time to clock high 30 Data-in hold time from clock high 31 Clock low to data-out valid (CPU writes data, control, or direction) MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor J92 J94 J93 J95 Table 13. Parallel I/O Timing Characteristic CPM Electrical Characteristics ...

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... Figure 39. IDMA External Requests Timing Diagram MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev Figure 39 Table 14. IDMA Controller Timing Characteristic Figure 42. All Frequencies Unit Min Max 7.00 — ns 3.00 — ns — 12.00 ns — 12.00 ns — 20.00 ns — 15.00 ns 7.00 — Freescale Semiconductor ...

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... CLKOUT (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 40. SDACK Timing Diagram—Peripheral Write, TA Sampled Low at the Falling Edge MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor the Clock CPM Electrical Characteristics 43 ...

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... SDACK Figure 41. SDACK Timing Diagram—Peripheral Write, TA Sampled High at the Falling Edge CLKOUT (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 42. SDACK Timing Diagram—Peripheral Read MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev the Clock 42 45 Freescale Semiconductor ...

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... TIN/TGATE rise and fall time 62 TIN/TGATE low time 63 TIN/TGATE high time 64 TIN/TGATE cycle time 65 CLKO high to TOUT valid MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Figure Table 15. Baud Rate Generator Timing All Frequencies Characteristic 40.00 40. Figure Table 16. Timer Timing ...

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... Table 17. SI Timing Characteristic Figure 49. All Frequencies Unit Min Max — SYNCCLK/2. MHz — — ns — 15.00 ns 20.00 — ns 35.00 — ns — 15.00 ns 17.00 — ns 13.00 — ns 10.00 45.00 ns 10.00 45.00 ns 10.00 45.00 ns 10.00 55.00 ns 10.00 55.00 ns 0.00 42.00 ns Freescale Semiconductor ...

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... CE=0) (Input) 71 L1RCLK (FE=1, CE=1) (Input) L1RSYNC (Input) 73 L1RxD (Input) L1ST n (Output) Figure 45. SI Receive Timing Diagram with Normal Clocking (DSC = 0) MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 17. SI Timing (continued) Characteristic 71a 72 RFSD BIT0 76 ...

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... CPM Electrical Characteristics L1RCLK (FE=1, CE=1) (Input) 82 L1RCLK (FE=0, CE=0) (Input) 75 L1RSYNC (Input L1RXD (Input) 76 L1ST(4-1) (Output) L1CLKO (Output) Figure 46. SI Receive Timing with Double-Speed Clocking (DSC = 1) MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev 83a RFSD=1 77 BIT0 Freescale Semiconductor ...

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... L1TCLK (FE=0, CE=0) (Input) 71 L1TCLK (FE=1, CE=1) (Input) 73 L1TSYNC (Input) L1TxD BIT0 (Output L1ST n (Output) MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 70 72 TFSD 80a Figure 47. SI Transmit Timing Diagram CPM Electrical Characteristics ...

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... CPM Electrical Characteristics L1RCLK (FE=0, CE=0) (Input) L1RCLK (FE=1, CE=1) (Input) L1RSYNC (Input) 73 L1TXD BIT0 (Output) 80 78a L1ST(4-1) (Output L1CLKO (Output) Figure 48. SI Transmit Timing with Double Speed Clocking (DSC = 1) MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev 83a 82 TFSD Freescale Semiconductor ...

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... MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Figure 49. IDL Timing CPM Electrical Characteristics 51 ...

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... All Frequencies Unit Min Max 0.00 SYNCCLK/3 MHz — — ns 0.00 30.00 ns 0.00 30.00 ns 40.00 — ns 40.00 — ns 0.00 — ns 40.00 — ns Freescale Semiconductor ...

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... TCLKx 102 TXDx (Output) RTSx (Output) CTSx (Input) CTSx (SYNC Input) Figure 51. SCC NMSI Transmit Timing Diagram MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 102 101 100 107 102 101 100 103 105 104 CPM Electrical Characteristics ...

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... Table 20. Ethernet Timing Characteristic 1 1 104 Figure 55. All Frequencies Unit Min Max 40.00 — ns — 15.00 ns 40.00 — ns 80.00 120.00 ns 20.00 — ns 5.00 — ns 10.00 — ns 100.00 — ns — 15.00 ns 40.00 — ns 99.00 101.00 ns 10.00 50.00 ns 10.00 50.00 ns 10.00 50.00 ns Freescale Semiconductor ...

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... CLSN(CTSx) (Input) Figure 53. Ethernet Collision Timing Diagram RCLKx RXDx (Input) RENA(CDx) (Input) Figure 54. Ethernet Receive Timing Diagram MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 20. Ethernet Timing (continued) Characteristic 2 2 120 121 121 124 125 CPM Electrical Characteristics ...

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... The ratio SyncCLK/SMCLKx must be greater or equal to 2/1. MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev 128 129 130 132 Figure 56. All Frequencies Characteristic 1 100.00 134 Unit Min Max — ns 50.00 — ns 50.00 — ns — 15.00 ns 10.00 50.00 ns 20.00 — ns 5.00 — ns Freescale Semiconductor ...

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... Master data valid (after SCK edge) 165 Master data hold time (outputs) 166 Rise time output 167 Fall time output MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 152 151 151a 150 NOTE 154 155 154 155 Figure 57 Table 22 ...

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... MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev 167 166 160 167 162 166 Data lsb 165 164 166 Data lsb 167 166 160 167 166 Data 165 msb Data msb msb lsb msb 164 166 lsb Freescale Semiconductor msb ...

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... Slave data valid (after SPICLK edge) 180 Slave data hold time (outputs) 181 Rise time (input) 182 Fall time (input) MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Figure 59 and Figure Table 23. SPI Slave Timing Characteristic CPM Electrical Characteristics 60. ...

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... SPIMOSI msb (Input) Figure 59. SPI Slave ( Timing Diagram MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev 172 182 181 170 181 182 180 Data lsb 179 181 182 Data lsb 171 174 178 Undef msb msb Freescale Semiconductor ...

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... Start condition setup time 206 Start condition hold time 207 Data hold time 208 Data setup time 209 SDL/SCL rise time MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 172 170 182 181 181 182 180 msb Data ...

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... Figure 61 Bus Timing Diagram ) CONTINUED All Frequencies Unit Min Max — 300.00 ns µs 4.70 — All Frequencies Unit Max 0 BRGCLK/48 Hz BRGCLK/48 Hz — s — s — s — s — — s — s — 1/(10 * fSCL) s — 1/(33 * fSCL) s — s 208 211 Freescale Semiconductor ...

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... The original pin numbering of the MPC850 conformed to a Freescale proprietary pin numbering scheme that has since been replaced by the JEDEC pin numbering standard for this package type. To support MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Table 26. MPC850 Family Derivatives 32-Channel HDLC ...

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... IRQ0 M D12 D13 D23 D4 D1 D27 K D11 D10 D9 D17 J D15 D14 D22 D18 D16 D5 G D25 D20 D19 VDDL F D21 D6 D28 D24 VDDH E D29 D7 D26 D31 D DP1 DP2 D30 CLKOUT C RSTCONF WAITB DP0 DP3 N/C B XFC VDDSYN A VSSSYN1 VSSSYN Freescale Semiconductor ...

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... For more information on the printed circuit board layout of the PBGA package, including thermal via design and suggested pad layout, please refer to AN-1231/D, Plastic Ball Grid Array Application Note available from your local Freescale sales office. MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor TCK PB24 PB23 ...

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... SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C. 4. PRIMARY DATUM C AND THE SEATING PLANE ARE MILLIMETERS DIM MIN MAX A 1.91 2.35 A1 0.50 0.70 A2 1.12 1.22 A3 0.29 0.43 b 0.60 0.90 D 23.00 BSC D1 19.05 REF D2 19.00 20.00 E 23.00 BSC E1 19.05 REF E2 19.00 20.00 e 1.27 BSC Freescale Semiconductor ...

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... JEDEC package dimensions of the PBGA. 0.20 C 256X 0. 0. SEATING PLANE SIDE VIEW 15X (E1) 4X Figure 65. Package Dimensions for the Plastic Ball Grid Array (PBGA)—JEDEC Standard MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor TOP VIEW B (D1) e 15X ...

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... Added footnote 3 to Table 5 (previously Table 4.5) and deleted IOL limit. Added MPC850DSL. Corrected Figure 25 on page 34. Updated power numbers and added Rev. C Removed reference to 5 Volt tolerance capability on peripheral interface pins. Replaced SI and IDL timing diagrams with better images. Updated to new template, added this revision table. Freescale Semiconductor ...

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... THIS PAGE INTENTIONALLY LEFT BLANK MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Document Revision History 69 ...

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... Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... THIS PAGE INTENTIONALLY LEFT BLANK MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor Document Revision History 71 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...