PRIXP425BC Intel, PRIXP425BC Datasheet - Page 111

IC NETWRK PROCESSR 400MHZ 492BGA

PRIXP425BC

Manufacturer Part Number
PRIXP425BC
Description
IC NETWRK PROCESSR 400MHZ 492BGA
Manufacturer
Intel
Datasheets

Specifications of PRIXP425BC

Processor Type
Network
Features
XScale Core
Speed
400MHz
Voltage
1.3V
Mounting Type
Surface Mount
Package / Case
492-BGA
Core Operating Frequency
400MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
869083

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PRIXP425BC
Manufacturer:
INTEL
Quantity:
20 000
Datasheet
Table 65.
5.6
Reset Timings Table Parameters
NOTES:
Power Sequence
The 3.3-V I/O voltage (V
IXP42X product line and IXC1100 control plane processors’ core voltage (V
become stable prior to the 3.3-V I/O voltage (V
voltages follow the V
value for T
V
line and IXC1100 control plane processors.
T
T
T
T
T
T
1. T
2. The expansion bus address is captured as a derivative of the RESET_IN_N signal going high. When a
3. PLL_LOCK is deasserted immediately when watchdog timer event occurs, or when RESET_IN_N is
RELEASE_PWRON_RST_N
RELEASE_RESET_IN_N
PLL_LOCK
EX_ADDR_SETUP
EX_ADDR_HOLD
WARM_RESET
CCP
oscillator is being used in place of a crystal, the 500-ms delay is not required.
programmable-logic device is used to drive the EX_ADDR signals instead of pull-downs, the signals must be
active until PLL_LOCK is active.
asserted, or when PWRON_RST_N is asserted. PLL_LOCK remains deasserted for ~24 ref_clocks after the
watchdog reset is deasserted (internal to the chip). A ref clock time period is 1/CLKIN.
RELEASE_PWRON_RST_N
at 3.3 V and V
Symbol
POWER_UP
CC
Intel
CC
must be at least 1
Minimum time required to hold the
PWRON_RST_N at logic 0 state after
stable power has been applied to the
IXP42X product line and IXC1100 control
plane processors. When using a crystal
to drive the processors’ system clock.
(OSC_IN and OSC_OUT)
Minimum time required to hold the
RESET_IN_N at logic 0 state after
PWRON_RST_N has been released to a
logic 1 state. The RESET_IN_N signal
must be held low when the
PWRON_RST_N signal is held low.
Maximum time for PLL_LOCK signal to
drive to logic 1 after RESET_IN_N is
driven to logic 1 state. The boot
sequence does not occur until this period
is complete.
Minimum time for the EX_ADDR signals
to drive the inputs prior to RESET_IN_N
being driven to logic 1 state. This is used
for sampling configuration information.
Minimum/maximum time for the
EX_ADDR signals to drive the inputs
prior to PLL_LOCK being driven to logic 1
state. This is used for sampling
configuration information.
Minimum time required to drive
RESET_IN_N signal to logic 0 in order to
cause a reset after the IXP42X product
line and IXC1100 control plane
processors has been in normal operation.
The power must remain stable and the
PWRON_RST_N signal must remain
stable.
at 1.3 V. There are no power-down requirements for the IXP42X product
power-up pattern. The V
is the time required for the internal oscillator to reach stability. When an external
CCP
®
IXP42X Product Line and IXC1100 Control Plane Processor
) must be powered up 1
Parameter
µ
s. The T
CCP
CCOSCP
POWER_UP
). The V
µs
before the core voltage (V
follows the V
CCOSC
timing parameter is measured from
Min.
500
500
10
50
0
, V
CCPLL1
Typ.
Electrical Specifications
CCP
power-up pattern. The
, and V
Max.
CC
10
20
) must never
CC
CCPLL2
Units
). The
ms
µs
ns
ns
ns
ns
Note
111
1
2
2

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