MC68HC000RC8 Freescale Semiconductor, MC68HC000RC8 Datasheet - Page 131

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MC68HC000RC8

Manufacturer Part Number
MC68HC000RC8
Description
IC MPU 32BIT 8MHZ 68-PGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC000RC8

Processor Type
M680x0 32-Bit
Speed
8MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
*The size of the index register (Xn) does not affect execution time.
9.3 STANDARD INSTRUCTION EXECUTION TIMES
The numbers of clock periods shown in tables 9-6 and 9-7 indicate the times required to
perform the operations, store the results, and read the next instruction. The total number
of clock periods, the number of read cycles, and the number of write cycles are shown in
the previously described format. The number of clock periods, the number of read cycles,
and the number of write cycles, respectively, must be added to those of the effective
address calculation where indicated by a plus sign (+).
In Tables 9-6 and 9-7, the following notation applies:
9-4
Dn
An
(An)
(An)+
–(An)
(d 16 , An)
(d 8 , An, Xn)*
(xxx).W
(xxx).L
(d 16 , PC)
(d 8 , PC, Xn)*
#<data>
Dn
An
(An)
(An)+
–(An)
An — Address register operand
Sn — Data register operand
ea — An operand specified by an effective address
M
Source
Source
— Memory effective address operand
Table 9-5. Move Long Instruction Loop Mode Execution Times
12(3/0)
12(3/0)
14(3/0)
16(4/0)
18(4/0)
16(4/0)
20(5/0)
16(4/0)
18(4/0)
12(3/0)
4(1/0)
4(1/0)
14(0/2)
14(0/2)
22(2/2)
22(2/2)
24(2/2)
Dn
(An)
Valid Count, cc False
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Table 9-4. Move Long Instruction Execution Times
Loop Continued
12(3/0)
12(3/0)
14(3/0)
16(4/0)
18(4/0)
16(4/0)
20(5/0)
16(4/0)
18(4/0)
12(3/0)
4(1/0)
4(1/0)
An
14(0/2)
14(0/2)
22(2/2)
22(2/2)
24(2/2)
(An)+
Freescale Semiconductor, Inc.
For More Information On This Product,
12(1/2)
12(1/2)
20(3/2)
20(3/2)
22(3/2)
24(4/2)
26(4/2)
24(4/2)
28(5/2)
24(4/2)
26(4/2)
20(3/2)
(An)
24(2/2)
24(2/2)
26(2/2)
–(An)
Go to: www.freescale.com
12(1/2)
12(1/2)
20(3/2)
20(3/2)
22(3/2)
24(4/2)
26(4/2)
24(4/2)
28(5/2)
24(4/2)
26(4/2)
20(3/2)
(An)+
20(2/2)
20(2/2)
28(4/2)
28(4/2)
30(4/2)
(An)
14(1/2)
14(1/2)
20(3/2)
20(3/2)
22(3/2)
24(4/2)
26(4/2)
24(4/2)
28(5/2)
24(4/2)
26(4/2)
20(3/2)
–(An)
Valid count, cc True
Destination
Destination
20(2/2)
20(2/2)
28(4/2)
28(4/2)
30(4/2)
(An)+
(d 16 , An)
16(2/2)
16(2/2)
24(4/2)
24(4/2)
26(4/2)
28(5/2)
30(5/2)
28(5/2)
32(6/2)
28(5/2)
30(5/2)
24(4/2)
30(4/2)
30(4/2)
32(4/2)
Loop Terminated
–(An)
(d 8 , An, Xn)*
18(2/2)
18(2/2)
26(4/2)
26(4/2)
28(4/2)
30(5/2)
32(5/2)
30(5/2)
34(6/2)
30(5/2)
32(5/2)
26(4/2)
18(2/2)
18(2/2)
24(4/2)
24(4/2)
26(4/2)
(An)
Expired Count
(xxx).W
18(2/2)
18(2/2)
24(4/2)
24(4/2)
26(4/2)
16(2/2)
16(2/2)
24(4/2)
24(4/2)
26(4/2)
28(5/2)
30(5/2)
28(5/2)
32(6/2)
28(5/2)
30(5/2)
24(4/2)
(An)+
MOTOROLA
26(4/2)
26(4/2)
28(4/2)
(xxx).L
20(3/2)
20(3/2)
28(5/2)
28(5/2)
30(5/2)
32(6/2)
34(6/2)
32(6/2)
36(7/2)
32(5/2)
34(6/2)
28(5/2)
–(An)

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