MC68HC000RC8 Freescale Semiconductor, MC68HC000RC8 Datasheet - Page 52

• Manufacturer Part Number: MC68HC000RC8
• Description: IC MPU 32BIT 8MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000RC8

• Processor Type: M680x0 32-Bit
• Speed: 8MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

The descriptions of the eight states of a write cycle are as follows:
STATE 0
STATE 1
STATE 2
STATE 3
STATE 4
STATE 5
STATE 6
5-6
FC2–FC0
*INTERNAL SIGNAL ONLY
D15–D8
A23–A1
DTACK
D7–D0
UDS
CLK
LDS
R/W
A0
AS
*
The write cycle starts in S0. The processor places valid function codes on
FC2–FC0 and drives R/W high (if a preceding write cycle has left R/W low).
During S3, the data bus is driven out of the high-impedance state as the
data to be written is placed on the bus.
At the rising edge of S4, the processor asserts U D S , or LDS. The
processor waits for a cycle termination signal (DTACK or BERR) or VPA, an
M6800 peripheral signal. When VPA is asserted during S4, the cycle
becomes a peripheral cycle (refer to Appendix B M6800 Peripheral
Interface. If neither termination signal is asserted before the falling
edge at the end of S4, the processor inserts wait states (full clock cycles)
until either DTACK or BERR is asserted.
During S5, no bus signals are altered.
During S6, no bus signals are altered.
Entering S1, the processor drives a valid address on the address bus.
On the rising edge of S2, the processor asserts AS and drives R/W low.
Figure 5-7. Word and Byte Write-Cycle Timing Diagram
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
WORD WRITE
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
ODD BYTE WRITE
EVEN BYTE WRITE
MOTOROLA