MC68HC000RC10 Freescale Semiconductor, MC68HC000RC10 Datasheet - Page 157

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MC68HC000RC10

Manufacturer Part Number
MC68HC000RC10
Description
IC MPU 32BIT 10MHZ 68-PGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC000RC10

Processor Type
M680x0 32-Bit
Speed
10MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC000RC10
Manufacturer:
TI
Quantity:
780
10.12 AC ELECTRICAL SPECIFICATIONS — BUS ARBITRATION
*These specifications represent improvement over previously published specifications for the 8-, 10-, and 12.5-MHz
** Applies only to the MC68HC000 and MC68HC001.
NOTES:
MOTOROLA
37A 2
58A 1
Num
MC68000 and are valid only for product bearing date codes of 8827 and later.
36 1
57A
58 1
16
33
34
35
37
38
39
46
47
57
7
1. Setup time for the synchronous inputs BGACK , IPL0 - IPL2 , and VPA guarantees their recognition at the
2. BR need fall at this time only in order to insure being recognized at the end of the bus cycle.
3. Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts,
4. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before
5. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may
VDC 5%; GND=0 VDC, T A =T L TO T H ; See Figure s 10-7 – 10-11) (Applies To All Processors
Except The MC68EC000)
Clock High to Address, Data
Bus High Impedance
(Maximum)
Clock High to Control Bus
High Impedance
Clock High to BG Asserted
Clock High to BG Negated
BR Asserted to BG Asserted
BR Negated to BG Negated
BGACK Asserted to BG
Negated
BGACK Asserted to BR
Negated
BG Asserted to Control,
Address, Data Bus High
Impedance (AS Negated)
BG Width Negated
BGACK Width Low
Asynchronous Input Setup
Time
BGACK Negated to AS, DS ,
R/ W Driven
BGACK Negated to FC, VMA
Driven
BR Negated to AS , DS, R/ W
Driven
BR Negated to FC, VMA
Driven
next falling edge of the clock.
unless otherwise noted. The voltage swing through this range should start outside and pass through the
range such that the rise or fall will be lienar between 0.8 volt and 2.0 volts.
asserting BGACK.
be reasserted.
Characteristic
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
For More Information On This Product,
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
20
10
1
1
8 MHz*
Go to: www.freescale.com
Max
Clks
3.5
3.5
3.5
1.5
80
80
62
80
62
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
20
10
10 MHz*
1
1
Max
Clks
3.5
3.5
3.5
1.5
70
70
50
50
70
12.5 MHz*
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
20
10
1
1
Max
Clks
3.5
3.5
3.5
1.5
60
60
40
40
60
16.67 MHz
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
10
0
0
5
1
1
12F
Max
Clks
3.5
3.5
3.5
1.5
40
50
50
50
40
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
10
0
0
5
1
1
16 MHz
Max
Clks
3.5
3.5
3.5
1.5
50
50
30
30
50
(V CC =5.0
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
10
20 MHz
0
0
5
1
1
10-17
Max
Clks
3.5
3.5
3.5
1.5
42
42
25
25
42
••
Clks/
Unit
Clks
Clks
Clks
Clks
Clks
Clks
Clks
Clks
Clks
ns
ns
ns
ns
ns
ns
ns

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