MC68HC000RC10 Freescale Semiconductor, MC68HC000RC10 Datasheet - Page 165

• Manufacturer Part Number: MC68HC000RC10
• Description: IC MPU 32BIT 10MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000RC10

• Processor Type: M680x0 32-Bit
• Speed: 10MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

31 2 , 5 DTACK Asserted to Data-In Valid
48 2 , 3 BERR Asserted to DTACK
NOTES:1. For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the
MOTOROLA
Num
58A 7 BR Negated to FC, VMA Driven
29A
36 7
47 5
56 4
58 7
29
30
32
33
34
35
38
39
44
53
55
AS, DS Negated to Data-In Invalid
(Hold Time on Read)
AS, DS Negated to Data-In High
Impedance
AS, DS Negated to BERR
Negated
(Setup Time)
HALT and RESET Input Transition
Time
Clock High to BG Asserted
Clock High to BG Negated
BR Asserted to BG Asserted
BR Negated to BG Negated
BG Asserted to Control, Address,
Data Bus High Impedance (AS
Negated)
BG Width Negated
AS, DS Negated to VPA Negated
Asynchronous Input Setup Time
Asserted
Data-Out Hold from Clock High
R/ W Asserted to Data Bus
Impedance Change
HALT/RESET Pulse Width
BR Negated to AS, DS, R/ W
Driven
2. Actual value depends on clock period.
3.I f #47 is satisfied for both DTACK and BERR , #48 may be ignored. In the absence of DTACK, BERR is an
4. For power-up, the MC68EC000 must be held in the reset state for 520 clocks to allow stabilization of on-
5. If the asynchronous input setup time (#47) requirement is satisfied for DTACK, the DTACK -asserted to data
6. When AS and R/W are equally loaded ( 20;pc), subtract 5 ns from the values given in these columns.
7. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded,
8. DS is used in this specification to indicate UDS and LDS .
maximum columns.
asynchronous input using the asynchronous input setup time (#47).
chip circuitry. After the system is powered up, #56 refers to the minimum pulse width required to
reset the processor.
setup time (#31) requirement can be ignored. The data must only satisfy the data-in to clock low
setup time (#27) for the following clock cycle.
BG may be reasserted.
Characteristic
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
For More Information On This Product,
Min
Go to: www.freescale.com
1.5
1.5
1.5
1.5
—
—
—
—
—
20
30
10
0
0
0
0
5
0
1
8 MHz
Max
187
150
3.5
3.5
—
—
90
35
35
55
55
—
—
—
—
—
—
—
Min
1.5
1.5
1.5
1.5
—
—
—
—
—
20
20
10
0
0
0
0
5
0
1
10 MHz
Max
150
150
3.5
3.5
—
—
65
35
35
55
55
—
—
—
—
—
—
—
Min
1.5
1.5
1.5
1.5
12.5 MHz
—
—
—
—
—
20
10
10
0
0
0
0
5
0
1
Max
120
150
3.5
3.5
—
—
50
35
55
55
—
—
—
—
—
—
—
35
Min
16.67 MHz
1.5
1.5
1.5
1.5
—
—
—
10
10
0
0
0
0
0
0
5
0
0
1
Max
150
3.5
3.5
90
50
30
30
50
50
—
—
—
—
—
—
—
—
—
Min
1.5
1.5
1.5
1.5
—
—
—
10
10
0
0
0
0
0
0
5
0
0
1
20 MHz
Max
150
3.5
3.5
—
75
—
42
25
25
42
—
42
—
—
—
—
—
—
—
10-25
Unit
Clks
Clks
Clks
Clks
Clks
Clks
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns