MC68HC000RC10 Freescale Semiconductor, MC68HC000RC10 Datasheet - Page 182

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MC68HC000RC10

Manufacturer Part Number
MC68HC000RC10
Description
IC MPU 32BIT 10MHZ 68-PGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC000RC10

Processor Type
M680x0 32-Bit
Speed
10MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC000RC10
Manufacturer:
TI
Quantity:
780
APPENDIX A
MC68010 LOOP MODE OPERATION
In the loop mode of the MC68010, a single instruction is executed repeatedly under
control of the test condition, decrement, and branch (DBcc) instruction without any
instruction fetch bus cycles. The execution of a single-instruction loop without fetching an
instruction provides a highly efficient means of repeating an instruction because the only
bus cycles required are those that read and write the operands.
The DBcc instruction uses three operands: a loop counter, a branch condition, and a
branch displacement. When this instruction is executed in the loop mode, the value in the
low-order word of the register specified as the loop counter is decremented by one and
compared to minus one. If the result after decrementing the value is equal to minus one,
the result is placed in the loop counter, and the next instruction in sequence is executed.
Otherwise, the condition code register is checked against the specified branch condition. If
the branch condition is true, the result is discarded, and the next instruction in sequence is
executed. When the count is not equal to minus one and the branch condition is false, the
branch displacement is added to the value in the program counter, and the instruction at
the resulting address is executed.
Figure A-1 shows the source code of a program fragment containing a loop that executes
in the loop mode in the MC68010. The program moves a block of data at address
SOURCE to a block starting at address DEST. The number of words in the block is
labeled LENGTH. If any word in the block at address SOURCE contains zero, the move
operation stops, and the program performs whatever processing follows this program
fragment.
LOOP
The first load effective address (LEA) instruction loads the address labeled SOURCE into
address register A0. The second instruction, also an LEA instruction, loads the address
labeled DEST into address register A1. Next, a move data from source to destination
(MOVE) instruction moves the number of words into data register D0, the loop counter.
The last two instructions, a MOVE and a test equal, decrement, and branch (DBEQ), form
the loop that moves the block of data. The bus activity required to execute these
instructions consists of the following cycles:
MOTOROLA
LEA
LEA
MOVE.W
MOVE.W
DBEQ
M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL
Figure A-1. DBcc Loop Mode Program Example
Freescale Semiconductor, Inc.
For More Information On This Product,
SOURCE, A0
DEST, A1
#LENGTH, D0
(A0);pl, (A1)+
D0, LOOP
Go to: www.freescale.com
Load A Pointer To Source Data
Load A Pointer To Destination
Load The Counter Register
Loop To Move The Block Of Data
Stop If Data Word Is Zero
A- 1

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