MC68HC000RC10 Freescale Semiconductor, MC68HC000RC10 Datasheet - Page 54

• Manufacturer Part Number: MC68HC000RC10
• Description: IC MPU 32BIT 10MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000RC10

• Processor Type: M680x0 32-Bit
• Speed: 10MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

The descriptions of the read-modify-write cycle states are as follows:
STATE 0
STATE 1
STATE 2
STATE 3
STATE 4
STATE 5
STATE 6
STATE 7
STATES 8–11
5-8
UDS OR LDS
FC2–FC0
D15–D8
A23–A1
DTACK
CLK
R/W
AS
The read cycle starts in S0. The processor places valid function codes on
FC2–FC0 and drives R/W high to identify a read cycle.
During S3, no bus signals are altered.
BERR) or VPA, an M6800 peripheral signal. When VPA is asserted during
S4, the cycle becomes a peripheral cycle (refer to Appendix B M6800
Peripheral Interface). If neither termination signal is asserted before the
falling edge at the end of S4, the processor inserts wait states (full clock
cycles) until either DTACK or BERR is asserted.
During S5, no bus signals are altered.
On the falling edge of the clock entering S7, the processor accepts data
from the device and negates U D S , and LDS. The device negates
DTACK or BERR at this time.
The bus signals are unaltered during S8–S11, during which the arithmetic
logic unit makes appropriate modifications to the data.
Entering S1, the processor drives a valid address on the address bus.
On the rising edge of S2, the processor asserts AS and UDS, or LDS.
During S4, the processor waits for a cycle termination signal (DTACK or
During S6, data from the device are driven onto the data bus.
Figure 5-9. Read-Modify-Write Cycle Timing Diagram
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
S0 S1 S2 S3 S4 S5 S6
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S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19
INDIVISIBLE CYCLE
MOTOROLA