MC68HC000RC10 Freescale Semiconductor, MC68HC000RC10 Datasheet - Page 69

• Manufacturer Part Number: MC68HC000RC10
• Description: IC MPU 32BIT 10MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000RC10

• Processor Type: M680x0 32-Bit
• Speed: 10MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

5.4. BUS ERROR AND HALT OPERATION
In a bus architecture that requires a handshake from an external device, such as the
asynchronous bus used in the M68000 Family, the handshake may not always occur. A
bus error input is provided to terminate a bus cycle in error when the expected signal is
not asserted. Different systems and different devices within the same system require
different maximum-response times. External circuitry can be provided to assert the bus
error signal after the appropriate delay following the assertion of address strobe.
In a virtual memory system, the bus error signal can be used to indicate either a page fault
or a bus timeout. An external memory management unit asserts bus error when the page
that contains the required data is not resident in memory. The processor suspends
execution of the current instruction while the page is loaded into memory. The MC68010
pushes enough information on the stack to be able to resume execution of the instruction
following return from the bus error exception handler.
MOTOROLA
FC2–FC0
BGACK
D15–D0
A23–A1
DTACK
UDS
R/W
LDS
CLK
BR
BG
AS
Figure 5-24. 2-Wire Bus Arbitration Timing Diagram—Special Case
BUS THREE-STATED
BG ASSERTED
BR VALID INTERNAL
BR SAMPLED
BR ASSERTED
S0
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
PROCESSOR
S2
Freescale Semiconductor, Inc.
For More Information On This Product,
S4
S6
Go to: www.freescale.com
BUS RELEASED FROM THREE STATE AND
PROCESSOR STARTS NEXT BUS CYCLE
BR NEGATED INTERNAL
BR SAMPLED
BR NEGATED
ALTERNATE BUS MASTER
S0
S2
PROCESSOR
S4
S6
S0
5- 23