MC68HC000RC10 Freescale Semiconductor, MC68HC000RC10 Datasheet - Page 74

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MC68HC000RC10

Manufacturer Part Number
MC68HC000RC10
Description
IC MPU 32BIT 10MHZ 68-PGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC000RC10

Processor Type
M680x0 32-Bit
Speed
10MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC000RC10
Manufacturer:
TI
Quantity:
780
While the processor is halted, the address bus and the data bus signals are placed in the
high-impedance state. Bus arbitration is performed as usual. Should a bus error occur
while HALT is asserted, the processor performs the retry operation previously described.
The single-step mode is derived from correctly timed transitions of HALT. HALT is negated
to allow the processor to begin a bus cycle, then asserted to enter the halt mode when the
cycle completes. The single-step mode proceeds through a program one bus cycle at a
time for debugging purposes. The halt operation and the hardware trace capability allow
tracing of either bus cycles or instructions one at a time. These capabilities and a software
debugging package provide total debugging flexibility.
5.4.4 Double Bus Fault
When a bus error exception occurs, the processor begins exception processing by
stacking information on the supervisor stack. If another bus error occurs during exception
processing (i.e., before execution of another instruction begins) the processor halts and
asserts HALT. This is called a double bus fault. Only an external reset operation can
restart a processor halted due to a double bus fault.
A retry operation does not initiate exception processing; a bus error during a retry
operation does not cause a double bus fault. The processor can continue to retry a bus
cycle indefinitely if external hardware requests.
5-28
FC2–FC0
D0–D15
A23–A1
DTACK
BERR
HALT
UDS
LDS
R/W
CLK
AS
S0
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
S2
Figure 5-29. Halt Operation Timing Diagram
Freescale Semiconductor, Inc.
READ
S4
For More Information On This Product,
S6
Go to: www.freescale.com
HALT
S0
S2
RETRY
S4
S6
MOTOROLA

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